* [PATCH 0/2] BXT basic slice/subslice/EU stuff @ 2015-03-31 16:59 jeff.mcgee 2015-03-31 16:59 ` [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info jeff.mcgee 2015-03-31 16:59 ` [PATCH 2/2] drm/i915/bxt: Add BXT HW status to SSEU status jeff.mcgee 0 siblings, 2 replies; 7+ messages in thread From: jeff.mcgee @ 2015-03-31 16:59 UTC (permalink / raw) To: intel-gfx From: Jeff McGee <jeff.mcgee@intel.com> These patches are dependent on the initial BXT enabling set from Imre, particularly the IS_BROXTON macro. Jeff McGee (2): drm/i915/bxt: Determine BXT slice/subslice/EU info drm/i915/bxt: Add BXT HW status to SSEU status drivers/gpu/drm/i915/i915_debugfs.c | 35 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_dma.c | 47 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 3 files changed, 85 insertions(+) -- 2.3.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info 2015-03-31 16:59 [PATCH 0/2] BXT basic slice/subslice/EU stuff jeff.mcgee @ 2015-03-31 16:59 ` jeff.mcgee 2015-04-01 6:20 ` Daniel Vetter 2015-03-31 16:59 ` [PATCH 2/2] drm/i915/bxt: Add BXT HW status to SSEU status jeff.mcgee 1 sibling, 1 reply; 7+ messages in thread From: jeff.mcgee @ 2015-03-31 16:59 UTC (permalink / raw) To: intel-gfx From: Jeff McGee <jeff.mcgee@intel.com> BXT uses a subset of the SKL fuse registers, because it has at most 1 slice and at most 6 EU per subslice. Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index ec661fe..81afd31 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -733,6 +733,53 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; info->has_subslice_pg = 0; info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; + } else if (IS_BROXTON(dev)) { + const int ss_max = 4; + int ss; + u32 fuse2, eu_disable, ss_disable; + + fuse2 = I915_READ(GEN8_FUSE2); + ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> + GEN9_F2_SS_DIS_SHIFT; + eu_disable = I915_READ(GEN8_EU_DISABLE0); + + info->slice_total = 1; + info->subslice_per_slice = ss_max - hweight32(ss_disable); + info->subslice_total = info->subslice_per_slice; + + /* + * Iterate through enabled subslices to count the total + * enabled EU. + */ + for (ss = 0; ss < ss_max; ss++) { + if (ss_disable & (0x1 << ss)) + /* skip disabled subslice */ + continue; + + /* + * BXT can have at most 6 EU per subslice. So only the + * lowest 6 bits of the 8-bit EU disable field are + * valid. + */ + info->eu_total += 6 - hweight8((eu_disable >> + (ss * 8)) & 0x3f); + } + + /* + * BXT expected to always have a uniform distribution of EU + * across subslices. + */ + info->eu_per_subslice = info->subslice_total ? + info->eu_total / info->subslice_total : + 0; + /* + * BXT supports subslice power gating on devices with more than + * one subslice, and supports EU power gating on devices with + * more than one EU pair per subslice. + */ + info->has_slice_pg = 0; + info->has_subslice_pg = (info->subslice_total > 1); + info->has_eu_pg = (info->eu_per_subslice > 2); } DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total); -- 2.3.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info 2015-03-31 16:59 ` [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info jeff.mcgee @ 2015-04-01 6:20 ` Daniel Vetter 2015-04-02 21:50 ` Jeff McGee 0 siblings, 1 reply; 7+ messages in thread From: Daniel Vetter @ 2015-04-01 6:20 UTC (permalink / raw) To: jeff.mcgee; +Cc: intel-gfx On Tue, Mar 31, 2015 at 09:59:22AM -0700, jeff.mcgee@intel.com wrote: > From: Jeff McGee <jeff.mcgee@intel.com> > > BXT uses a subset of the SKL fuse registers, because it has at > most 1 slice and at most 6 EU per subslice. > > Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> > --- > drivers/gpu/drm/i915/i915_dma.c | 47 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index ec661fe..81afd31 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -733,6 +733,53 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; > info->has_subslice_pg = 0; > info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; > + } else if (IS_BROXTON(dev)) { By all reasonable standards this function is getting a bit too long. Can you please create a patch to extract the various platform-specific sseu detection logic. Also can't we just repurpose the skl version by limiting s_max appropriately and applying diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 68e0c85a17cf..b164aeb09158 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -668,9 +668,8 @@ static void intel_device_info_runtime_init(struct drm_device *dev) ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> GEN9_F2_SS_DIS_SHIFT; - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0); - eu_disable[1] = I915_READ(GEN8_EU_DISABLE1); - eu_disable[2] = I915_READ(GEN8_EU_DISABLE2); + for (s = 0; s < s_max; s++) + eu_disable[s] = I915_READ(GEN8_EU_DISABLE(s)); info->slice_total = hweight32(s_enable); with a suitable added #define ofc? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info 2015-04-01 6:20 ` Daniel Vetter @ 2015-04-02 21:50 ` Jeff McGee 2015-04-07 8:22 ` Daniel Vetter 0 siblings, 1 reply; 7+ messages in thread From: Jeff McGee @ 2015-04-02 21:50 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx On Wed, Apr 01, 2015 at 08:20:44AM +0200, Daniel Vetter wrote: > On Tue, Mar 31, 2015 at 09:59:22AM -0700, jeff.mcgee@intel.com wrote: > > From: Jeff McGee <jeff.mcgee@intel.com> > > > > BXT uses a subset of the SKL fuse registers, because it has at > > most 1 slice and at most 6 EU per subslice. > > > > Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> > > --- > > drivers/gpu/drm/i915/i915_dma.c | 47 +++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 47 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > > index ec661fe..81afd31 100644 > > --- a/drivers/gpu/drm/i915/i915_dma.c > > +++ b/drivers/gpu/drm/i915/i915_dma.c > > @@ -733,6 +733,53 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > > info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; > > info->has_subslice_pg = 0; > > info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; > > + } else if (IS_BROXTON(dev)) { > > By all reasonable standards this function is getting a bit too long. Can > you please create a patch to extract the various platform-specific sseu > detection logic. > > Also can't we just repurpose the skl version by limiting s_max > appropriately and applying > > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 68e0c85a17cf..b164aeb09158 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -668,9 +668,8 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> > GEN9_F2_SS_DIS_SHIFT; > > - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0); > - eu_disable[1] = I915_READ(GEN8_EU_DISABLE1); > - eu_disable[2] = I915_READ(GEN8_EU_DISABLE2); > + for (s = 0; s < s_max; s++) > + eu_disable[s] = I915_READ(GEN8_EU_DISABLE(s)); > > info->slice_total = hweight32(s_enable); > > with a suitable added #define ofc? > -Daniel Agree with all of the above. Regarding the 2nd patch in this series which performs related logic in i915_debugfs, would you like to see that broken up similarly? -Jeff _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info 2015-04-02 21:50 ` Jeff McGee @ 2015-04-07 8:22 ` Daniel Vetter 0 siblings, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2015-04-07 8:22 UTC (permalink / raw) To: Daniel Vetter, intel-gfx On Thu, Apr 02, 2015 at 02:50:09PM -0700, Jeff McGee wrote: > On Wed, Apr 01, 2015 at 08:20:44AM +0200, Daniel Vetter wrote: > > On Tue, Mar 31, 2015 at 09:59:22AM -0700, jeff.mcgee@intel.com wrote: > > > From: Jeff McGee <jeff.mcgee@intel.com> > > > > > > BXT uses a subset of the SKL fuse registers, because it has at > > > most 1 slice and at most 6 EU per subslice. > > > > > > Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_dma.c | 47 +++++++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 47 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > > > index ec661fe..81afd31 100644 > > > --- a/drivers/gpu/drm/i915/i915_dma.c > > > +++ b/drivers/gpu/drm/i915/i915_dma.c > > > @@ -733,6 +733,53 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > > > info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; > > > info->has_subslice_pg = 0; > > > info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; > > > + } else if (IS_BROXTON(dev)) { > > > > By all reasonable standards this function is getting a bit too long. Can > > you please create a patch to extract the various platform-specific sseu > > detection logic. > > > > Also can't we just repurpose the skl version by limiting s_max > > appropriately and applying > > > > > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > > index 68e0c85a17cf..b164aeb09158 100644 > > --- a/drivers/gpu/drm/i915/i915_dma.c > > +++ b/drivers/gpu/drm/i915/i915_dma.c > > @@ -668,9 +668,8 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > > ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> > > GEN9_F2_SS_DIS_SHIFT; > > > > - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0); > > - eu_disable[1] = I915_READ(GEN8_EU_DISABLE1); > > - eu_disable[2] = I915_READ(GEN8_EU_DISABLE2); > > + for (s = 0; s < s_max; s++) > > + eu_disable[s] = I915_READ(GEN8_EU_DISABLE(s)); > > > > info->slice_total = hweight32(s_enable); > > > > with a suitable added #define ofc? > > -Daniel > > Agree with all of the above. Regarding the 2nd patch in this series which > performs related logic in i915_debugfs, would you like to see that broken > up similarly? Yeah I think the same rework would benefit the debugfs code too, if only for consistency. Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915/bxt: Add BXT HW status to SSEU status 2015-03-31 16:59 [PATCH 0/2] BXT basic slice/subslice/EU stuff jeff.mcgee 2015-03-31 16:59 ` [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info jeff.mcgee @ 2015-03-31 16:59 ` jeff.mcgee 2015-04-09 8:22 ` shuang.he 1 sibling, 1 reply; 7+ messages in thread From: jeff.mcgee @ 2015-03-31 16:59 UTC (permalink / raw) To: intel-gfx From: Jeff McGee <jeff.mcgee@intel.com> BXT uses the same power gate control ack message registers as SKL. BXT makes use of additional fields which indicate the power gating state of each subslice in BXT's single slice. Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 35 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 007c7d7..6c5ba28 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4566,6 +4566,41 @@ static int i915_sseu_status(struct seq_file *m, void *unused) eu_per = max(eu_per, eu_cnt); } } + } else if (IS_BROXTON(dev)) { + const int ss_max = 3; + int ss; + u32 s_reg, eu_reg[2], eu_mask[2]; + + s_reg = I915_READ(GEN9_SLICE0_PGCTL_ACK); + eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK); + eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK); + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | + GEN9_PGCTL_SSA_EU19_ACK | + GEN9_PGCTL_SSA_EU210_ACK | + GEN9_PGCTL_SSA_EU311_ACK; + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | + GEN9_PGCTL_SSB_EU19_ACK | + GEN9_PGCTL_SSB_EU210_ACK | + GEN9_PGCTL_SSB_EU311_ACK; + + if (s_reg & GEN9_PGCTL_SLICE_ACK) { + + s_tot = 1; + for (ss = 0; ss < ss_max; ss++) { + unsigned int eu_cnt; + + if (!(s_reg & (GEN9_PGCTL_SS0_ACK << (2 * ss)))) + /* skip disabled subslice */ + continue; + + ss_per++; + eu_cnt = 2 * hweight32(eu_reg[ss/2] & + eu_mask[ss%2]); + eu_tot += eu_cnt; + eu_per = max(eu_per, eu_cnt); + } + } + ss_tot = ss_per; } seq_printf(m, " Enabled Slice Total: %u\n", s_tot); seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7e1a0fd9..be6554f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6275,6 +6275,9 @@ enum skl_disp_power_wells { #define GEN9_SLICE1_PGCTL_ACK 0x8050 #define GEN9_SLICE2_PGCTL_ACK 0x8054 #define GEN9_PGCTL_SLICE_ACK (1 << 0) +#define GEN9_PGCTL_SS0_ACK (1 << 2) /* Only for SLICE0 */ +#define GEN9_PGCTL_SS1_ACK (1 << 4) /* Only for SLICE0 */ +#define GEN9_PGCTL_SS2_ACK (1 << 6) /* Only for SLICE0 */ #define GEN9_SLICE0_SS01_EU_PGCTL_ACK 0x805c #define GEN9_SLICE0_SS23_EU_PGCTL_ACK 0x8060 -- 2.3.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915/bxt: Add BXT HW status to SSEU status 2015-03-31 16:59 ` [PATCH 2/2] drm/i915/bxt: Add BXT HW status to SSEU status jeff.mcgee @ 2015-04-09 8:22 ` shuang.he 0 siblings, 0 replies; 7+ messages in thread From: shuang.he @ 2015-04-09 8:22 UTC (permalink / raw) To: shuang.he, ethan.gao, intel-gfx, jeff.mcgee Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) Task id: 6105 -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 313/313 313/313 IVB 337/337 337/337 BYT 286/286 286/286 HSW 395/395 395/395 BDW 321/321 321/321 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-04-09 8:22 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-03-31 16:59 [PATCH 0/2] BXT basic slice/subslice/EU stuff jeff.mcgee 2015-03-31 16:59 ` [PATCH 1/2] drm/i915/bxt: Determine BXT slice/subslice/EU info jeff.mcgee 2015-04-01 6:20 ` Daniel Vetter 2015-04-02 21:50 ` Jeff McGee 2015-04-07 8:22 ` Daniel Vetter 2015-03-31 16:59 ` [PATCH 2/2] drm/i915/bxt: Add BXT HW status to SSEU status jeff.mcgee 2015-04-09 8:22 ` shuang.he
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