Re: [PATCH 15/19] drm/i915: HSW cdclk support

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 15/19] drm/i915: HSW cdclk support
Date: Tue, 7 Apr 2015 11:28:11 +0300	[thread overview]
Message-ID: <20150407082811.GF17410@intel.com> (raw)
In-Reply-To: <552378CB.7@intel.com>

On Tue, Apr 07, 2015 at 11:57:23AM +0530, Sivakumar Thulasimani wrote:
> 
> 
> On 3/31/2015 4:44 PM, Mika Kahola wrote:
> > Implement support for changing the cdclk frequency during runtime on
> > HSW. VLV/CHV already have support for this, so we can follow their
> > example for the most part. Only the actual hardware programming differs,
> > the rest is pretty much the same.
> >
> > The pipe pixel rate stuff is handled a bit differently for now due to
> > the difference in pch vs. gmch pfit handling. Eventually we should unify
> > that part to eliminate what is essentially duplicated code.
> >
> > v2: Grab rps.hw_lock around sandybridge_pcode_write()
> > v3: Rebase due to power well vs. .global_resources() reordering
> > v4: Rebase due to .global_resources() reordering for Haswell
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h      |   3 +
> >   drivers/gpu/drm/i915/intel_display.c | 161 ++++++++++++++++++++++++++++++++++-
> >   2 files changed, 161 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f26ebd2..b25f712 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6244,6 +6244,7 @@ enum skl_disp_power_wells {
> >   #define   GEN6_PCODE_WRITE_D_COMP		0x11
> >   #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
> >   #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> > +#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> >   #define   DISPLAY_IPS_CONTROL			0x19
> >   #define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> >   #define GEN6_PCODE_DATA				0x138128
> > @@ -6698,10 +6699,12 @@ enum skl_disp_power_wells {
> >   #define  LCPLL_PLL_LOCK			(1<<30)
> >   #define  LCPLL_CLK_FREQ_MASK		(3<<26)
> >   #define  LCPLL_CLK_FREQ_450		(0<<26)
> > +#define  LCPLL_CLK_FREQ_ALT_HSW		(1<<26) /* 337.5 (ULX) or 540 */
> >   #define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)
> >   #define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)
> >   #define  LCPLL_CLK_FREQ_675_BDW		(3<<26)
> >   #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
> > +#define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1<<24)
> >   #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
> >   #define  LCPLL_POWER_DOWN_ALLOW		(1<<22)
> >   #define  LCPLL_CD_SOURCE_FCLK		(1<<21)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3752d5e..cce7103 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5012,7 +5012,16 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> >   {
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> >   
> > -	if (IS_VALLEYVIEW(dev)) {
> > +	if (IS_HASWELL(dev)) {
> > +		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> > +			dev_priv->max_cdclk_freq = 450000;
> > +		else if (IS_HSW_ULX(dev))
> > +			dev_priv->max_cdclk_freq = 337500;
> > +		else if (IS_HSW_ULT(dev))
> > +			dev_priv->max_cdclk_freq = 450000;
> > +		else
> > +			dev_priv->max_cdclk_freq = 540000;
> > +	} else if (IS_VALLEYVIEW(dev)) {
> >   		dev_priv->max_cdclk_freq = 400000;
> >   	} else {
> >   		/* otherwise assume cdclk is fixed */
> > @@ -8773,6 +8782,144 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
> >   	hsw_disable_lcpll(dev_priv, true, true);
> >   }
> >   
> > +/* compute the max rate for new configuration */
> > +static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
> > +{
> > +	struct drm_device *dev = dev_priv->dev;
> > +	struct intel_crtc *crtc;
> > +	int max_pixel_rate = 0;
> > +
> > +	for_each_intel_crtc(dev, crtc) {
> > +		if (crtc->new_enabled)
> > +			max_pixel_rate = max(max_pixel_rate,
> > +					     ilk_pipe_pixel_rate(crtc->new_config));
> > +	}
> > +
> > +	return max_pixel_rate;
> > +}
> > +
> > +static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
> > +			      int max_pixel_rate)
> > +{
> > +	int cdclk;
> > +
> > +	/*
> > +	 * FIXME should also account for plane ratio
> > +	 * once 64bpp pixel formats are supported.
> > +	 */
> > +	if (max_pixel_rate > 450000)
> > +		cdclk = 540000;
> > +	else if (max_pixel_rate > 337500 || !IS_HSW_ULX(dev_priv))
> > +		cdclk = 450000;
> > +	else
> > +		cdclk = 337500;
> > +
> > +	/*
> > +	 * FIXME move the cdclk caclulation to
> > +	 * compute_config() so we can fail gracegully.
> > +	 */
> > +	if (cdclk > dev_priv->max_cdclk_freq) {
> > +		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> > +			  cdclk, dev_priv->max_cdclk_freq);
> > +		cdclk = dev_priv->max_cdclk_freq;
> > +	}
> > +
> > +	return cdclk;
> > +}
> won't this return 337MHz even for platforms that have HSW_CDCLK_LIMIT is 
> set ? this should return 450MHz if this fuse is set

I'm not sure ULX machines would ever have HSW_CDCLK_LIMIT set. But
having a check for it should do no harm so might as well I suppose.

-- 
Ville Syrjälä
Intel OTC
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