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From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 41/70] drm/i915: Tidy gen8 IRQ handler
Date: Fri, 10 Apr 2015 10:36:49 +0200	[thread overview]
Message-ID: <20150410083649.GA12038@phenom.ffwll.local> (raw)
In-Reply-To: <1428420094-18352-42-git-send-email-chris@chris-wilson.co.uk>

On Tue, Apr 07, 2015 at 04:21:05PM +0100, Chris Wilson wrote:
> Remove some needless variables and parameter passing.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Merged 3 patches up to this one, thanks.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 113 +++++++++++++++++-----------------------
>  1 file changed, 49 insertions(+), 64 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c2c80bf490c6..46bcbff89760 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -985,8 +985,7 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev)
>  	return;
>  }
>  
> -static void notify_ring(struct drm_device *dev,
> -			struct intel_engine_cs *ring)
> +static void notify_ring(struct intel_engine_cs *ring)
>  {
>  	if (!intel_ring_initialized(ring))
>  		return;
> @@ -1248,9 +1247,9 @@ static void ilk_gt_irq_handler(struct drm_device *dev,
>  {
>  	if (gt_iir &
>  	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
> -		notify_ring(dev, &dev_priv->ring[RCS]);
> +		notify_ring(&dev_priv->ring[RCS]);
>  	if (gt_iir & ILK_BSD_USER_INTERRUPT)
> -		notify_ring(dev, &dev_priv->ring[VCS]);
> +		notify_ring(&dev_priv->ring[VCS]);
>  }
>  
>  static void snb_gt_irq_handler(struct drm_device *dev,
> @@ -1260,11 +1259,11 @@ static void snb_gt_irq_handler(struct drm_device *dev,
>  
>  	if (gt_iir &
>  	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
> -		notify_ring(dev, &dev_priv->ring[RCS]);
> +		notify_ring(&dev_priv->ring[RCS]);
>  	if (gt_iir & GT_BSD_USER_INTERRUPT)
> -		notify_ring(dev, &dev_priv->ring[VCS]);
> +		notify_ring(&dev_priv->ring[VCS]);
>  	if (gt_iir & GT_BLT_USER_INTERRUPT)
> -		notify_ring(dev, &dev_priv->ring[BCS]);
> +		notify_ring(&dev_priv->ring[BCS]);
>  
>  	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
>  		      GT_BSD_CS_ERROR_INTERRUPT |
> @@ -1275,63 +1274,65 @@ static void snb_gt_irq_handler(struct drm_device *dev,
>  		ivybridge_parity_error_irq_handler(dev, gt_iir);
>  }
>  
> -static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
> -				       struct drm_i915_private *dev_priv,
> +static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
>  				       u32 master_ctl)
>  {
> -	struct intel_engine_cs *ring;
> -	u32 rcs, bcs, vcs;
> -	uint32_t tmp = 0;
>  	irqreturn_t ret = IRQ_NONE;
>  
>  	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> -		tmp = I915_READ_FW(GEN8_GT_IIR(0));
> +		u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
>  		if (tmp) {
>  			I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
>  			ret = IRQ_HANDLED;
>  
> -			rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
> -			ring = &dev_priv->ring[RCS];
> -			if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
> -				intel_lrc_irq_handler(ring);
> -			if (rcs & GT_RENDER_USER_INTERRUPT)
> -				notify_ring(dev, ring);
> -
> -			bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
> -			ring = &dev_priv->ring[BCS];
> -			if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
> -				intel_lrc_irq_handler(ring);
> -			if (bcs & GT_RENDER_USER_INTERRUPT)
> -				notify_ring(dev, ring);
> +			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
> +				intel_lrc_irq_handler(&dev_priv->ring[RCS]);
> +			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
> +				notify_ring(&dev_priv->ring[RCS]);
> +
> +			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
> +				intel_lrc_irq_handler(&dev_priv->ring[BCS]);
> +			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
> +				notify_ring(&dev_priv->ring[BCS]);
>  		} else
>  			DRM_ERROR("The master control interrupt lied (GT0)!\n");
>  	}
>  
>  	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
> -		tmp = I915_READ_FW(GEN8_GT_IIR(1));
> +		u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
>  		if (tmp) {
>  			I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
>  			ret = IRQ_HANDLED;
>  
> -			vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
> -			ring = &dev_priv->ring[VCS];
> -			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
> -				intel_lrc_irq_handler(ring);
> -			if (vcs & GT_RENDER_USER_INTERRUPT)
> -				notify_ring(dev, ring);
> -
> -			vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
> -			ring = &dev_priv->ring[VCS2];
> -			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
> -				intel_lrc_irq_handler(ring);
> -			if (vcs & GT_RENDER_USER_INTERRUPT)
> -				notify_ring(dev, ring);
> +			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
> +				intel_lrc_irq_handler(&dev_priv->ring[VCS]);
> +			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
> +				notify_ring(&dev_priv->ring[VCS]);
> +
> +			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
> +				intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
> +			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
> +				notify_ring(&dev_priv->ring[VCS2]);
>  		} else
>  			DRM_ERROR("The master control interrupt lied (GT1)!\n");
>  	}
>  
> +	if (master_ctl & GEN8_GT_VECS_IRQ) {
> +		u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
> +		if (tmp) {
> +			I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
> +			ret = IRQ_HANDLED;
> +
> +			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
> +				intel_lrc_irq_handler(&dev_priv->ring[VECS]);
> +			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
> +				notify_ring(&dev_priv->ring[VECS]);
> +		} else
> +			DRM_ERROR("The master control interrupt lied (GT3)!\n");
> +	}
> +
>  	if (master_ctl & GEN8_GT_PM_IRQ) {
> -		tmp = I915_READ_FW(GEN8_GT_IIR(2));
> +		u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
>  		if (tmp & dev_priv->pm_rps_events) {
>  			I915_WRITE_FW(GEN8_GT_IIR(2),
>  				      tmp & dev_priv->pm_rps_events);
> @@ -1341,22 +1342,6 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
>  			DRM_ERROR("The master control interrupt lied (PM)!\n");
>  	}
>  
> -	if (master_ctl & GEN8_GT_VECS_IRQ) {
> -		tmp = I915_READ_FW(GEN8_GT_IIR(3));
> -		if (tmp) {
> -			I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
> -			ret = IRQ_HANDLED;
> -
> -			vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
> -			ring = &dev_priv->ring[VECS];
> -			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
> -				intel_lrc_irq_handler(ring);
> -			if (vcs & GT_RENDER_USER_INTERRUPT)
> -				notify_ring(dev, ring);
> -		} else
> -			DRM_ERROR("The master control interrupt lied (GT3)!\n");
> -	}
> -
>  	return ret;
>  }
>  
> @@ -1651,7 +1636,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
>  
>  	if (HAS_VEBOX(dev_priv->dev)) {
>  		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
> -			notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
> +			notify_ring(&dev_priv->ring[VECS]);
>  
>  		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
>  			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
> @@ -1845,7 +1830,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  			I915_WRITE(VLV_IIR, iir);
>  		}
>  
> -		gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> +		gen8_gt_irq_handler(dev_priv, master_ctl);
>  
>  		/* Call regardless, as some status bits might not be
>  		 * signalled in iir */
> @@ -2187,7 +2172,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  
>  	/* Find, clear, then process each source of interrupt */
>  
> -	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
> +	ret = gen8_gt_irq_handler(dev_priv, master_ctl);
>  
>  	if (master_ctl & GEN8_DE_MISC_IRQ) {
>  		tmp = I915_READ(GEN8_DE_MISC_IIR);
> @@ -3692,7 +3677,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
>  		new_iir = I915_READ16(IIR); /* Flush posted writes */
>  
>  		if (iir & I915_USER_INTERRUPT)
> -			notify_ring(dev, &dev_priv->ring[RCS]);
> +			notify_ring(&dev_priv->ring[RCS]);
>  
>  		for_each_pipe(dev_priv, pipe) {
>  			int plane = pipe;
> @@ -3883,7 +3868,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
>  		new_iir = I915_READ(IIR); /* Flush posted writes */
>  
>  		if (iir & I915_USER_INTERRUPT)
> -			notify_ring(dev, &dev_priv->ring[RCS]);
> +			notify_ring(&dev_priv->ring[RCS]);
>  
>  		for_each_pipe(dev_priv, pipe) {
>  			int plane = pipe;
> @@ -4110,9 +4095,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>  		new_iir = I915_READ(IIR); /* Flush posted writes */
>  
>  		if (iir & I915_USER_INTERRUPT)
> -			notify_ring(dev, &dev_priv->ring[RCS]);
> +			notify_ring(&dev_priv->ring[RCS]);
>  		if (iir & I915_BSD_USER_INTERRUPT)
> -			notify_ring(dev, &dev_priv->ring[VCS]);
> +			notify_ring(&dev_priv->ring[VCS]);
>  
>  		for_each_pipe(dev_priv, pipe) {
>  			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
> -- 
> 2.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-04-10  8:34 UTC|newest]

Thread overview: 113+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-07 15:20 Low hanging fruit take 2 Chris Wilson
2015-04-07 15:20 ` [PATCH 01/70] drm/i915: Cache last obj->pages location for i915_gem_object_get_page() Chris Wilson
2015-04-08 11:16   ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 02/70] drm/i915: Fix the flip synchronisation to consider mmioflips Chris Wilson
2015-04-07 15:20 ` [PATCH 03/70] drm/i915: Ensure cache flushes prior to doing CS flips Chris Wilson
2015-04-08 11:23   ` Daniel Vetter
2015-04-08 11:29     ` Chris Wilson
2015-04-07 15:20 ` [PATCH 04/70] drm/i915: Agressive downclocking on Baytrail Chris Wilson
2015-04-07 15:20 ` [PATCH 05/70] drm/i915: Fix computation of last_adjustment for RPS autotuning Chris Wilson
2015-04-07 15:20 ` [PATCH 06/70] drm/i915: Fix race on unreferencing the wrong mmio-flip-request Chris Wilson
2015-04-08 11:30   ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 07/70] drm/i915: Boost GPU frequency if we detect outstanding pageflips Chris Wilson
2015-04-08 11:31   ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 08/70] drm/i915: Deminish contribution of wait-boosting from clients Chris Wilson
2015-04-07 15:20 ` [PATCH 09/70] drm/i915: Re-enable RPS wait-boosting for all engines Chris Wilson
2015-04-07 15:20 ` [PATCH 10/70] drm/i915: Split i915_gem_batch_pool into its own header Chris Wilson
2015-04-07 15:20 ` [PATCH 11/70] drm/i915: Tidy batch pool logic Chris Wilson
2015-04-07 15:20 ` [PATCH 12/70] drm/i915: Split the batch pool by engine Chris Wilson
2015-04-07 15:20 ` [PATCH 13/70] drm/i915: Free batch pool when idle Chris Wilson
2015-04-07 15:20 ` [PATCH 14/70] drm/i915: Split batch pool into size buckets Chris Wilson
2015-04-07 15:20 ` [PATCH 15/70] drm/i915: Include active flag when describing objects in debugfs Chris Wilson
2015-04-08 11:33   ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 16/70] drm/i915: Suppress empty lines from debugfs/i915_gem_objects Chris Wilson
2015-04-08 11:34   ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 17/70] drm/i915: Optimistically spin for the request completion Chris Wilson
2015-04-08 11:39   ` Daniel Vetter
2015-04-08 13:43     ` Rantala, Valtteri
2015-04-08 14:15       ` Daniel Vetter
2015-04-13 11:34   ` Tvrtko Ursulin
2015-04-13 12:25     ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 18/70] drm/i915: Implement inter-engine read-read optimisations Chris Wilson
2015-04-14 13:51   ` Tvrtko Ursulin
2015-04-14 14:00     ` Chris Wilson
2015-04-07 15:20 ` [PATCH 19/70] drm/i915: Inline check required for object syncing prior to execbuf Chris Wilson
2015-04-07 15:20 ` [PATCH 20/70] drm/i915: Limit ring synchronisation (sw sempahores) RPS boosts Chris Wilson
2015-04-08 11:46   ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 21/70] drm/i915: Limit mmio flip " Chris Wilson
2015-04-07 15:20 ` [PATCH 22/70] drm/i915: Reduce frequency of unspecific HSW reg debugging Chris Wilson
2015-04-07 15:20 ` [PATCH 23/70] drm/i915: Record ring->start address in error state Chris Wilson
2015-04-08 11:47   ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 24/70] drm/i915: Use simpler form of spin_lock_irq(execlist_lock) Chris Wilson
2015-04-07 15:20 ` [PATCH 25/70] drm/i915: Use the global runtime-pm wakelock for a busy GPU for execlists Chris Wilson
2015-04-07 15:20 ` [PATCH 26/70] drm/i915: Map the execlists context regs once during pinning Chris Wilson
2015-04-07 15:20 ` [PATCH 27/70] drm/i915: Remove vestigal DRI1 ring quiescing code Chris Wilson
2015-04-09 15:02   ` Daniel Vetter
2015-04-09 15:24     ` Chris Wilson
2015-04-09 15:31       ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 28/70] drm/i915: Overhaul execlist submission Chris Wilson
2015-04-07 15:20 ` [PATCH 29/70] drm/i915: Move the execlists retirement to the right spot Chris Wilson
2015-04-07 15:20 ` [PATCH 30/70] drm/i915: Map the ringbuffer using WB on LLC machines Chris Wilson
2015-04-07 15:20 ` [PATCH 31/70] drm/i915: Refactor duplicate object vmap functions Chris Wilson
2015-04-07 15:20 ` [PATCH 32/70] drm/i915: Treat ringbuffer writes as write to normal memory Chris Wilson
2015-04-07 15:20 ` [PATCH 33/70] drm/i915: Use a separate slab for requests Chris Wilson
2015-05-22 14:48   ` Robert Beckett
2015-04-07 15:20 ` [PATCH 34/70] drm/i915: Use a separate slab for vmas Chris Wilson
2015-04-10  8:32   ` Daniel Vetter
2015-04-07 15:20 ` [PATCH 35/70] drm/i915: Use the new rq->i915 field where appropriate Chris Wilson
2015-04-07 15:21 ` [PATCH 36/70] drm/i915: Reduce the pointer dance of i915_is_ggtt() Chris Wilson
2015-04-07 15:21 ` [PATCH 37/70] drm/i915: Squash more pointer indirection for i915_is_gtt Chris Wilson
2015-04-07 15:21 ` [PATCH 38/70] drm/i915: Reduce locking in execlist command submission Chris Wilson
2015-04-07 15:21 ` [PATCH 39/70] drm/i915: Reduce more " Chris Wilson
2015-04-07 15:21 ` [PATCH 40/70] drm/i915: Reduce locking in gen8 IRQ handler Chris Wilson
2015-04-07 15:21 ` [PATCH 41/70] drm/i915: Tidy " Chris Wilson
2015-04-10  8:36   ` Daniel Vetter [this message]
2015-04-07 15:21 ` [PATCH 42/70] drm/i915: Remove request retirement before each batch Chris Wilson
2015-04-07 15:21 ` [PATCH 43/70] drm/i915: Cache the GGTT offset for the execlists context Chris Wilson
2015-04-07 15:21 ` [PATCH 44/70] drm/i915: Prefer to check for idleness in worker rather than sync-flush Chris Wilson
2015-04-10  8:37   ` Daniel Vetter
2015-04-07 15:21 ` [PATCH 45/70] drm/i915: Remove request->uniq Chris Wilson
2015-04-10  8:38   ` Daniel Vetter
2015-04-07 15:21 ` [PATCH 46/70] drm/i915: Cache the reset_counter for the request Chris Wilson
2015-04-07 15:21 ` [PATCH 47/70] drm/i915: Allocate context objects from stolen Chris Wilson
2015-04-10  8:39   ` Daniel Vetter
2015-04-07 15:21 ` [PATCH 48/70] drm/i915: Introduce an internal allocator for disposable private objects Chris Wilson
2015-04-07 15:21 ` [PATCH 49/70] drm/i915: Do not zero initialise page tables Chris Wilson
2015-04-07 15:21 ` [PATCH 50/70] drm/i915: The argument for postfix is redundant Chris Wilson
2015-04-10  8:53   ` Daniel Vetter
2015-04-10  9:00     ` Chris Wilson
2015-04-10  9:32       ` Daniel Vetter
2015-04-10  9:45         ` Chris Wilson
2015-04-07 15:21 ` [PATCH 51/70] drm/i915: Record the position of the start of the request Chris Wilson
2015-04-07 15:21 ` [PATCH 52/70] drm/i915: Cache the execlist ctx descriptor Chris Wilson
2015-04-07 15:21 ` [PATCH 53/70] drm/i915: Eliminate vmap overhead for cmd parser Chris Wilson
2015-04-07 15:21 ` [PATCH 54/70] drm/i915: Cache last cmd descriptor when parsing Chris Wilson
2015-04-07 15:21 ` [PATCH 55/70] drm/i915: Use WC copies on !llc platforms for the command parser Chris Wilson
2015-04-07 15:21 ` [PATCH 56/70] drm/i915: Cache kmap between relocations Chris Wilson
2015-04-07 15:21 ` [PATCH 57/70] drm/i915: intel_ring_initialized() must be simple and inline Chris Wilson
2015-12-08 15:02   ` [PATCH 0/1] " Dave Gordon
2015-12-08 15:02     ` [PATCH 1/1] " Dave Gordon
2015-12-10 10:24       ` Daniel Vetter
2015-04-07 15:21 ` [PATCH 58/70] drm/i915: Before shrink_all we only need to idle the GPU Chris Wilson
2015-04-07 15:21 ` [PATCH 59/70] drm/i915: Simplify object is-pinned checking for shrinker Chris Wilson
2015-04-07 16:28 ` Chris Wilson
2015-04-07 16:28   ` [PATCH 60/70] drm/i915: Make evict-everything more robust Chris Wilson
2015-04-07 16:28   ` [PATCH 61/70] drm/i915: Make fb_tracking.lock a spinlock Chris Wilson
2015-04-14 14:52     ` Tvrtko Ursulin
2015-04-14 15:05       ` Chris Wilson
2015-04-14 15:15         ` Tvrtko Ursulin
2015-04-07 16:28   ` [PATCH 62/70] drm/i915: Reduce locking inside busy ioctl Chris Wilson
2015-04-07 16:28   ` [PATCH 63/70] drm/i915: Reduce locking inside swfinish ioctl Chris Wilson
2015-04-10  9:14     ` Daniel Vetter
2015-04-15  9:03       ` Chris Wilson
2015-04-15  9:33         ` Daniel Vetter
2015-04-15  9:38           ` Chris Wilson
2015-04-07 16:28   ` [PATCH 64/70] drm/i915: Remove pinned check from madvise ioctl Chris Wilson
2015-04-07 16:28   ` [PATCH 65/70] drm/i915: Reduce locking for gen6+ GT interrupts Chris Wilson
2015-04-07 16:28   ` [PATCH 66/70] drm/i915: Remove obj->pin_mappable Chris Wilson
2015-04-13 11:35     ` Tvrtko Ursulin
2015-04-13 12:30       ` Daniel Vetter
2015-04-07 16:28   ` [PATCH 67/70] drm/i915: Start passing around i915_vma from execbuffer Chris Wilson
2015-04-07 16:28   ` [PATCH 68/70] drm/i915: Simplify vma-walker for i915_gem_objects Chris Wilson
2015-04-07 16:28   ` [PATCH 69/70] drm/i915: Skip holding an object reference for execbuf preparation Chris Wilson
2015-04-07 16:28   ` [PATCH 70/70] drm/i915: Use vma as the primary token for managing binding Chris Wilson

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