Re: [PATCH v3 3/8] drm/i915/skl: Add DC5 Trigger Sequence

From: Damien Lespiau <damien.lespiau@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: Suketu Shah <suketu.j.shah@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 3/8] drm/i915/skl: Add DC5 Trigger Sequence
Date: Mon, 13 Apr 2015 18:49:19 +0100	[thread overview]
Message-ID: <20150413174918.GE5156@strange.ger.corp.intel.com> (raw)
In-Reply-To: <1428920783-23802-1-git-send-email-animesh.manna@intel.com>

On Mon, Apr 13, 2015 at 03:56:23PM +0530, Animesh Manna wrote:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 90e47a9..8d6deaa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -667,6 +667,12 @@ struct intel_uncore {
>  #define for_each_fw_domain(domain__, dev_priv__, i__) \
>  	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
>  
> +enum csr_states {
> +	FW_LOADED = 0,
> +	FW_LOADING,
> +	FW_FAILED
> +};
> +
>  struct intel_csr {
>  	const char *fw_path;
>  	__be32 *dmc_payload;
> @@ -674,6 +680,7 @@ struct intel_csr {
>  	uint32_t mmio_count;
>  	uint32_t mmioaddr[8];
>  	uint32_t mmiodata[8];
> +	enum csr_states states;
>  };

Usually these kind of enum and variable are singular. enum csr_state and
state.

-- 
Damien
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