From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Mika Kahola <mika.kahola@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 13/14] drm/i915: Limit CHV max cdclk
Date: Wed, 15 Apr 2015 22:19:00 +0300 [thread overview]
Message-ID: <20150415191900.GM1237@intel.com> (raw)
In-Reply-To: <1429103244-3515-14-git-send-email-mika.kahola@intel.com>
On Wed, Apr 15, 2015 at 04:07:23PM +0300, Mika Kahola wrote:
> Limit CHV maximum cdclk to 320MHz.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 09f3518..d79421a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5239,7 +5239,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> else
> dev_priv->max_cdclk_freq = 540000;
> } else if (IS_VALLEYVIEW(dev)) {
> - dev_priv->max_cdclk_freq = 400000;
> + dev_priv->max_cdclk_freq = IS_CHERRYVIEW(dev) ? 320000 : 400000;
> } else {
> /* otherwise assume cdclk is fixed */
> dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2015-04-15 19:19 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-15 13:07 All sort of cdclk stuff Mika Kahola
2015-04-15 13:07 ` [PATCH 01/14] drm/i915: Fix i855 get_display_clock_speed Mika Kahola
2015-04-15 13:07 ` [PATCH 02/14] drm/i915: Fix 852GM/GMV cdclk Mika Kahola
2015-04-15 13:07 ` [PATCH 03/14] drm/i915: Add cdclk extraction for g33, g965gm and g4x Mika Kahola
2015-04-15 13:07 ` [PATCH 04/14] drm/i915: Warn when cdclk for the platforms is not known Mika Kahola
2015-04-15 13:07 ` [PATCH 05/14] drm/i915: Cache current cdclk frequency in dev_priv Mika Kahola
2015-04-15 13:07 ` [PATCH 06/14] drm/i915: Use cached cdclk value Mika Kahola
2015-04-15 13:07 ` [PATCH 07/14] drm/i915: Unify ilk and hsw .get_aux_clock_divider Mika Kahola
2015-04-15 13:07 ` [PATCH 08/14] drm/i915: Store max cdclk value in dev_priv Mika Kahola
2015-04-15 13:07 ` [PATCH 09/14] drm/i915: Don't enable IPS when pixel rate exceeds 95% Mika Kahola
2015-04-15 13:07 ` [PATCH 10/14] drm/i915: HSW cdclk support Mika Kahola
2015-04-15 13:07 ` [PATCH 11/14] drm/i915: Add IS_BDW_ULX Mika Kahola
2015-04-15 13:07 ` [PATCH 12/14] drm/i915: BDW clock change support Mika Kahola
2015-04-15 13:07 ` [PATCH 13/14] drm/i915: Limit CHV max cdclk Mika Kahola
2015-04-15 19:19 ` Ville Syrjälä [this message]
2015-04-15 13:07 ` [PATCH 14/14] drm/i915: Modeset global_pipes() update Mika Kahola
2015-04-15 19:19 ` Ville Syrjälä
2015-04-17 9:23 ` shuang.he
2015-04-15 13:16 ` All sort of cdclk stuff Damien Lespiau
2015-04-15 13:58 ` Mika Kahola
2015-04-15 14:18 ` Ville Syrjälä
2015-04-16 13:11 ` Jani Nikula
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