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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
	Mika Kahola <mika.kahola@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 05/12] drm/i915: Cache current cdclk frequency in dev_priv
Date: Thu, 16 Apr 2015 14:20:42 +0300	[thread overview]
Message-ID: <20150416112042.GP1237@intel.com> (raw)
In-Reply-To: <20150416110512.GB16653@nuc-i3427.alporthouse.com>

On Thu, Apr 16, 2015 at 12:05:12PM +0100, Chris Wilson wrote:
> On Thu, Apr 16, 2015 at 01:51:43PM +0300, Mika Kahola wrote:
> > On Thu, 2015-04-16 at 09:02 +0100, Chris Wilson wrote:
> > > On Thu, Apr 16, 2015 at 10:40:51AM +0300, Mika Kahola wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Rather that extracting the current cdclk freuqncy every time someone
> > > > wants to know it, cache the current value and use that. VLV/CHV already
> > > > stored a cached value there so just expand that to cover all platforms.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > V2: Rebased to the latest
> > > > 
> > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > 
> > > Which debugfs file shows this? Do we have one for the similar clock freqs?
> > > -Chris
> > > 
> > 
> > I don't think we have one for cdclk. Then again, should we add this to
> > debugfs?
> 
> Is it useful to know? Yes, it people have added it to userspace tools.
> It it derived, or variable state that we may get wrong, or are other
> calculations dependent on it such that we will want to know its value to
> check the results? Yes.

Such a file should probably show the pch/hrawclk, czclk, and perhaps
memory clock too (or maybe we have that somewhere already?).

I've had plans to clean up the rawclk stuff too to resemble the cdclk
handling a bit more. The rawclk shouldn't change at runtime though,
so it should be mostly a search and replaec operation. Though we might
want to extract it for real on VLV/CHV from CCK rather than just
assuming the 100MHz (which it will be though). Similar thing could be
done for czclk as well.

-- 
Ville Syrjälä
Intel OTC
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  reply	other threads:[~2015-04-16 11:20 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-16  7:40 [PATCH 00/12] All sort of cdclk stuff Mika Kahola
2015-04-16  7:40 ` [PATCH 01/12] drm/i915: Fix i855 get_display_clock_speed Mika Kahola
2015-04-16  7:40 ` [PATCH 02/12] drm/i915: Fix 852GM/GMV cdclk Mika Kahola
2015-04-16  7:40 ` [PATCH 03/12] drm/i915: Add cdclk extraction for g33, g965gm and g4x Mika Kahola
2015-04-16  7:40 ` [PATCH 04/12] drm/i915: Warn when cdclk for the platforms is not known Mika Kahola
2015-04-16  7:40 ` [PATCH 05/12] drm/i915: Cache current cdclk frequency in dev_priv Mika Kahola
2015-04-16  8:02   ` Chris Wilson
2015-04-16 10:51     ` Mika Kahola
2015-04-16 11:05       ` Chris Wilson
2015-04-16 11:20         ` Ville Syrjälä [this message]
2015-04-16  7:40 ` [PATCH 06/12] drm/i915: Use cached cdclk value Mika Kahola
2015-04-16  7:40 ` [PATCH 07/12] drm/i915: Unify ilk and hsw .get_aux_clock_divider Mika Kahola
2015-04-16  7:40 ` [PATCH 08/12] drm/i915: Store max cdclk value in dev_priv Mika Kahola
2015-04-16  7:40 ` [PATCH 09/12] drm/i915: Don't enable IPS when pixel rate exceeds 95% Mika Kahola
2015-04-16  7:40 ` [PATCH 10/12] drm/i915: HSW cdclk support Mika Kahola
2015-04-16  7:40 ` [PATCH 11/12] drm/i915: Add IS_BDW_ULX Mika Kahola
2015-04-16  7:40 ` [PATCH 12/12] drm/i915: BDW clock change support Mika Kahola
2015-04-16 23:33   ` shuang.he

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