From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/8] drm/i915: Merge the GEN9 memory latency PCU opcode with its friends
Date: Tue, 5 May 2015 21:54:55 +0300 [thread overview]
Message-ID: <20150505185455.GL18908@intel.com> (raw)
In-Reply-To: <1430408363-20905-5-git-send-email-damien.lespiau@intel.com>
On Thu, Apr 30, 2015 at 04:39:19PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Patches 2,3,4 satisfy my brain's visual pattern matcher.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 880290d..6d428a5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6642,6 +6642,11 @@ enum skl_disp_power_wells {
> #define GEN6_PCODE_READ_RC6VIDS 0x5
> #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
> #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
> +#define GEN9_PCODE_READ_MEM_LATENCY 0x6
> +#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
> +#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
> +#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
> +#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
> #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
> #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
> #define GEN6_READ_OC_PARAMS 0xc
> @@ -6655,12 +6660,6 @@ enum skl_disp_power_wells {
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> #define GEN6_PCODE_DATA1 0x13812C
>
> -#define GEN9_PCODE_READ_MEM_LATENCY 0x6
> -#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
> -#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
> -#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
> -#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
> -
> #define GEN6_GT_CORE_STATUS 0x138060
> #define GEN6_CORE_CPD_STATE_MASK (7<<4)
> #define GEN6_RCn_MASK 7
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2015-05-05 18:55 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-30 15:39 [PATCH 0/8] SKL suspend/resume Damien Lespiau
2015-04-30 15:39 ` [PATCH 1/8] drm/i915/skl: Add the INIT power domain to the MISC I/O power well Damien Lespiau
2015-05-05 18:54 ` Ville Syrjälä
2015-04-30 15:39 ` [PATCH 2/8] drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 defines Damien Lespiau
2015-04-30 15:39 ` [PATCH 3/8] drm/i915: Re-order the PCU opcodes Damien Lespiau
2015-04-30 15:39 ` [PATCH 4/8] drm/i915: Merge the GEN9 memory latency PCU opcode with its friends Damien Lespiau
2015-05-05 18:54 ` Ville Syrjälä [this message]
2015-04-30 15:39 ` [PATCH 5/8] drm/i915/skl: Make the Misc I/O power well part of the PLLS domain Damien Lespiau
2015-05-05 18:55 ` Ville Syrjälä
2015-04-30 15:39 ` [PATCH 6/8] drm/i915/skl: Deinit/init the display at suspend/resume Damien Lespiau
2015-05-05 18:56 ` Ville Syrjälä
2015-05-06 11:10 ` Ville Syrjälä
2015-05-06 10:52 ` Daniel Vetter
2015-04-30 15:39 ` [PATCH 7/8] drm/i915/skl: Change CDCLK behind PCU's back Damien Lespiau
2015-05-06 10:53 ` Daniel Vetter
2015-05-06 10:58 ` Damien Lespiau
2015-04-30 15:39 ` [PATCH 8/8] drm/i915/skl: gen6+ platforms support runtime PM Damien Lespiau
2015-05-02 8:20 ` shuang.he
2015-05-05 18:56 ` Ville Syrjälä
2015-05-06 10:54 ` Daniel Vetter
2015-05-06 10:55 ` Damien Lespiau
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