From: Daniel Vetter <daniel@ffwll.ch>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 7/8] drm/i915/skl: Change CDCLK behind PCU's back
Date: Wed, 6 May 2015 12:53:14 +0200 [thread overview]
Message-ID: <20150506105314.GT30184@phenom.ffwll.local> (raw)
In-Reply-To: <1430408363-20905-8-git-send-email-damien.lespiau@intel.com>
On Thu, Apr 30, 2015 at 04:39:22PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Why? I.e. way too terse commit message.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9c8338f..2cbae9a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5525,6 +5525,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
> {
> int ret;
> u32 val, freq_select, freq_decimal, pcu_ack;
> + bool do_pcu_ack = true;
>
> DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
>
> @@ -5534,8 +5535,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
> ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
> mutex_unlock(&dev_priv->rps.hw_lock);
> if (ret || !(val & SKL_CDCLK_READY_FOR_CHANGE)) {
> - DRM_ERROR("failed to inform PCU about cdclk change\n");
> - return;
> + DRM_DEBUG_KMS("failed to inform PCU about cdclk change\n");
> + do_pcu_ack = false;
> }
>
> /* set CDCLK_CTL */
> @@ -5567,6 +5568,9 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
> I915_WRITE(CDCLK_CTL, freq_select | freq_decimal);
> POSTING_READ(CDCLK_CTL);
>
> + if (!do_pcu_ack)
> + return;
> +
> /* inform PCU of the change */
> mutex_lock(&dev_priv->rps.hw_lock);
> sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Intel-gfx mailing list
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next prev parent reply other threads:[~2015-05-06 10:50 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-30 15:39 [PATCH 0/8] SKL suspend/resume Damien Lespiau
2015-04-30 15:39 ` [PATCH 1/8] drm/i915/skl: Add the INIT power domain to the MISC I/O power well Damien Lespiau
2015-05-05 18:54 ` Ville Syrjälä
2015-04-30 15:39 ` [PATCH 2/8] drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 defines Damien Lespiau
2015-04-30 15:39 ` [PATCH 3/8] drm/i915: Re-order the PCU opcodes Damien Lespiau
2015-04-30 15:39 ` [PATCH 4/8] drm/i915: Merge the GEN9 memory latency PCU opcode with its friends Damien Lespiau
2015-05-05 18:54 ` Ville Syrjälä
2015-04-30 15:39 ` [PATCH 5/8] drm/i915/skl: Make the Misc I/O power well part of the PLLS domain Damien Lespiau
2015-05-05 18:55 ` Ville Syrjälä
2015-04-30 15:39 ` [PATCH 6/8] drm/i915/skl: Deinit/init the display at suspend/resume Damien Lespiau
2015-05-05 18:56 ` Ville Syrjälä
2015-05-06 11:10 ` Ville Syrjälä
2015-05-06 10:52 ` Daniel Vetter
2015-04-30 15:39 ` [PATCH 7/8] drm/i915/skl: Change CDCLK behind PCU's back Damien Lespiau
2015-05-06 10:53 ` Daniel Vetter [this message]
2015-05-06 10:58 ` Damien Lespiau
2015-04-30 15:39 ` [PATCH 8/8] drm/i915/skl: gen6+ platforms support runtime PM Damien Lespiau
2015-05-02 8:20 ` shuang.he
2015-05-05 18:56 ` Ville Syrjälä
2015-05-06 10:54 ` Daniel Vetter
2015-05-06 10:55 ` Damien Lespiau
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