From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Sonika Jindal <sonika.jindal@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: Rename dp rates array as per platform
Date: Thu, 7 May 2015 11:35:40 +0300 [thread overview]
Message-ID: <20150507083540.GV18908@intel.com> (raw)
In-Reply-To: <1430972529-26279-2-git-send-email-sonika.jindal@intel.com>
On Thu, May 07, 2015 at 09:52:08AM +0530, Sonika Jindal wrote:
> Renaming gen9_rates to skl_rates because other platforms may have different
> supported rates.
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6bd5afb..c9d50d1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -84,8 +84,8 @@ static const struct dp_link_dpll chv_dpll[] = {
> { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> };
> -/* Skylake supports following rates */
> -static const int gen9_rates[] = { 162000, 216000, 270000,
> +
> +static const int skl_rates[] = { 162000, 216000, 270000,
> 324000, 432000, 540000 };
> static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> 243000, 270000, 324000, 405000,
> @@ -1161,9 +1161,9 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
> static int
> intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
> {
> - if (INTEL_INFO(dev)->gen >= 9) {
> - *source_rates = gen9_rates;
> - return ARRAY_SIZE(gen9_rates);
> + if (IS_SKYLAKE(dev)) {
> + *source_rates = skl_rates;
> + return ARRAY_SIZE(skl_rates);
> } else if (IS_CHERRYVIEW(dev)) {
> *source_rates = chv_rates;
> return ARRAY_SIZE(chv_rates);
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-05-07 8:35 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-07 4:22 [PATCH 1/3] drm/i915: Sink rate read should be saved in deca-kHz Sonika Jindal
2015-05-07 4:22 ` [PATCH 2/3] drm/i915: Rename dp rates array as per platform Sonika Jindal
2015-05-07 8:35 ` Ville Syrjälä [this message]
2015-05-07 13:19 ` Daniel Vetter
2015-05-07 4:22 ` [PATCH 3/3] drm/i915/bxt: edp1.4 Intermediate Freq support Sonika Jindal
2015-05-07 8:41 ` Ville Syrjälä
2015-05-07 8:57 ` Jindal, Sonika
2015-05-07 11:06 ` [PATCH] " Sonika Jindal
2015-05-07 15:34 ` Ville Syrjälä
2015-05-08 5:34 ` Sonika Jindal
2015-05-08 12:26 ` Ville Syrjälä
2015-05-11 7:51 ` Sonika Jindal
2015-05-11 9:51 ` Daniel Vetter
2015-05-14 13:30 ` shuang.he
2015-05-26 9:21 ` Sonika Jindal
2015-05-26 9:48 ` Daniel Vetter
2015-05-26 9:57 ` Jani Nikula
2015-05-26 9:59 ` Daniel Vetter
2015-05-26 10:21 ` Jindal, Sonika
2015-05-26 12:20 ` Sonika Jindal
2015-06-03 5:19 ` Jindal, Sonika
2015-06-03 6:31 ` Kannan, Vandana
2015-06-03 8:00 ` Jani Nikula
2015-05-26 9:54 ` Jani Nikula
2015-05-08 19:30 ` shuang.he
2015-05-08 7:39 ` shuang.he
2015-05-07 19:04 ` [PATCH 3/3] " shuang.he
2015-05-07 8:10 ` [PATCH 1/3] drm/i915: Sink rate read should be saved in deca-kHz Jani Nikula
2015-05-07 8:34 ` Ville Syrjälä
2015-05-07 8:29 ` [PATCH] " Sonika Jindal
2015-05-07 8:58 ` Jani Nikula
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