Re: [PATCH 4/4] drm/i915: Changes required to enable DSI Video Mode on CHT

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, May 12, 2015 at 05:20:41PM +0300, Jani Nikula wrote:
> From: Gaurav K Singh <gaurav.k.singh@intel.com>
> 
> On CHT, changes are required for calculating the correct m,n & p with
> minimal error +/- for the required DSI clock, so that the correct
> dividor & ctrl values are written in cck regs for DSI. This patch has
> been tested on CHT RVP with 1200 x 1920 panel.
> 
> v2 by Jani, rebased on earlier refactoring, original at [1].
> 
> [1] http://mid.gmane.org/1431368400-1942-5-git-send-email-rodrigo.vivi@intel.com
> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++++++++++++++++++++------
>  1 file changed, 20 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index d1aefc7a0629..686802b49b83 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -157,11 +157,13 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
>  
>  #endif
>  
> -static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp)
> +static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
> +			struct dsi_mnp *dsi_mnp, int target_dsi_clk)
>  {
>  	unsigned int calc_m = 0, calc_p = 0;
> -	unsigned int m, n = 1, p;
> -	int ref_clk = 25000;
> +	unsigned int m_min, m_max, p_min = 2, p_max = 6;
> +	unsigned int m, n, p;
> +	int ref_clk;
>  	int delta = target_dsi_clk;
>  	u32 m_seed;
>  
> @@ -171,8 +173,20 @@ static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp)
>  		return -ECHRNG;
>  	}
>  
> -	for (m = 62; m <= 92 && delta; m++) {
> -		for (p = 2; p <= 6 && delta; p++) {
> +	if (IS_CHERRYVIEW(dev_priv)) {
> +		ref_clk = 100000;
> +		n = 4;
> +		m_min = 70;
> +		m_max = 96;
> +	} else {
> +		ref_clk = 25000;
> +		n = 1;
> +		m_min = 62;
> +		m_max = 92;
> +	}

About the only thing I can actually verify from the specs is the refclk
change. As for the rest, well, it looks sane enough.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


> +
> +	for (m = m_min; m <= m_max && delta; m++) {
> +		for (p = p_min; p <= p_max && delta; p++) {
>  			/*
>  			 * Find the optimal m and p divisors with minimal delta
>  			 * +/- the required clock
> @@ -212,7 +226,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
>  				    intel_dsi->lane_count);
>  
> -	ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
> +	ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
>  	if (ret) {
>  		DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
>  		return;
> -- 
> 2.1.4

-- 
Ville Syrjälä
Intel OTC
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