From: Daniel Vetter <daniel@ffwll.ch>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/4 v3] drm/i915: Tighten the exposure ARGB/ABGR 8888 formats
Date: Tue, 19 May 2015 19:01:59 +0200 [thread overview]
Message-ID: <20150519170159.GS15256@phenom.ffwll.local> (raw)
In-Reply-To: <1432034956-562-1-git-send-email-damien.lespiau@intel.com>
On Tue, May 19, 2015 at 12:29:16PM +0100, Damien Lespiau wrote:
> ARGB8888 is used for cursors on all platforms so we need to allow it
> everywhere.
>
> ABGR8888 is currently only honoured:
> - on VLV/CHV in sprite planes
> - on SKL+ for primary and sprite planes
> so only allow it for those platforms.
>
> Note that we only support ARGB8888/ABGR8888 on the primary plane for
> SKL/BXT because we have in line of sight the pipe bottom color on those
> platforms and because the primary plane programming on VLV/CHV doesn't
> anything different for those formats today.
>
> v2: Fix the logic to forbid the creation ABGR2101010 fbs (Ville)
> v3: Still allow the creation of ARGB8888 fbs now that cursor planes use
> real fb objects (found by PRTS).
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Let's retry. Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++----------
> 1 file changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8a3d936..9d2d6fb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -51,7 +51,6 @@ static const uint32_t i8xx_primary_formats[] = {
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB1555,
> DRM_FORMAT_XRGB8888,
> - DRM_FORMAT_ARGB8888,
> };
>
> /* Primary plane formats for gen >= 4 */
> @@ -60,6 +59,15 @@ static const uint32_t i965_primary_formats[] = {
> DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> +};
> +
> +static const uint32_t skl_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> DRM_FORMAT_ARGB8888,
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> @@ -2704,11 +2712,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> dspcntr |= DISPPLANE_BGRX565;
> break;
> case DRM_FORMAT_XRGB8888:
> - case DRM_FORMAT_ARGB8888:
> dspcntr |= DISPPLANE_BGRX888;
> break;
> case DRM_FORMAT_XBGR8888:
> - case DRM_FORMAT_ABGR8888:
> dspcntr |= DISPPLANE_RGBX888;
> break;
> case DRM_FORMAT_XRGB2101010:
> @@ -2810,11 +2816,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> dspcntr |= DISPPLANE_BGRX565;
> break;
> case DRM_FORMAT_XRGB8888:
> - case DRM_FORMAT_ARGB8888:
> dspcntr |= DISPPLANE_BGRX888;
> break;
> case DRM_FORMAT_XBGR8888:
> - case DRM_FORMAT_ABGR8888:
> dspcntr |= DISPPLANE_RGBX888;
> break;
> case DRM_FORMAT_XRGB2101010:
> @@ -13293,12 +13297,15 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
> if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
> primary->plane = !pipe;
>
> - if (INTEL_INFO(dev)->gen <= 3) {
> - intel_primary_formats = i8xx_primary_formats;
> - num_formats = ARRAY_SIZE(i8xx_primary_formats);
> - } else {
> + if (INTEL_INFO(dev)->gen >= 9) {
> + intel_primary_formats = skl_primary_formats;
> + num_formats = ARRAY_SIZE(skl_primary_formats);
> + } else if (INTEL_INFO(dev)->gen >= 4) {
> intel_primary_formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
> + } else {
> + intel_primary_formats = i8xx_primary_formats;
> + num_formats = ARRAY_SIZE(i8xx_primary_formats);
> }
>
> drm_universal_plane_init(dev, &primary->base, 0,
> @@ -13985,8 +13992,14 @@ static int intel_framebuffer_init(struct drm_device *dev,
> return -EINVAL;
> }
> break;
> - case DRM_FORMAT_XBGR8888:
> case DRM_FORMAT_ABGR8888:
> + if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
> + DRM_DEBUG("unsupported pixel format: %s\n",
> + drm_get_format_name(mode_cmd->pixel_format));
> + return -EINVAL;
> + }
> + break;
> + case DRM_FORMAT_XBGR8888:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
> if (INTEL_INFO(dev)->gen < 4) {
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-05-19 16:59 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-15 18:05 [PATCH 0/4] Don't say we support framebuffers with alpha when we don't Damien Lespiau
2015-05-15 18:06 ` [PATCH 1/4] drm/i915: Remove the COMMON_PRIMARY_FORMATS defines Damien Lespiau
2015-05-15 18:41 ` Ville Syrjälä
2015-05-15 18:06 ` [PATCH 2/4] drm/i915: Remove ARBG/ABGR 2101010 on platform not supporting those formats Damien Lespiau
2015-05-15 18:44 ` Ville Syrjälä
2015-05-15 18:06 ` [PATCH 3/4] drm/i915: Don't expose RGB/BGR 8888 formats on primary planes before SKL Damien Lespiau
2015-05-15 18:56 ` Ville Syrjälä
2015-05-15 19:15 ` [PATCH v2] " Damien Lespiau
2015-05-19 8:00 ` Daniel Vetter
2015-05-19 11:29 ` [PATCH 3/4 v3] drm/i915: Tighten the exposure ARGB/ABGR 8888 formats Damien Lespiau
2015-05-19 17:01 ` Daniel Vetter [this message]
2015-05-15 18:06 ` [PATCH 4/4] drm/i915: Don't expose ARGB1555 on gen2/3 Damien Lespiau
2015-05-15 18:57 ` Ville Syrjälä
2015-05-18 8:34 ` Daniel Vetter
2015-05-18 14:57 ` shuang.he
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