From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/5] drm/i915: Store boot CDCLK in dev_priv on DDI platforms
Date: Thu, 21 May 2015 15:48:23 +0300 [thread overview]
Message-ID: <20150521124823.GB18908@intel.com> (raw)
In-Reply-To: <20150520155630.GJ15256@phenom.ffwll.local>
On Wed, May 20, 2015 at 05:56:30PM +0200, Daniel Vetter wrote:
> On Wed, May 20, 2015 at 05:53:42PM +0200, Daniel Vetter wrote:
> > On Wed, May 20, 2015 at 02:45:17PM +0100, Damien Lespiau wrote:
> > > Right not we don't initialize the stored CDCLK on DDI platforms. Fix
> > > that.
> > >
> > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> >
> > Merged up to this patch, thanks, Daniel
>
> I'll take that back, our usage of dev_priv->cdclk_freq seems rather
> inconsistent and there's patches in-flight to completely rework all this.
> Hence I dropped this patch here again.
dev_priv->cdclk_freq is going to be the current cdclk frequency. So if
we actually want to hang on to the boot cdclk it needs to be stored
separately.
> -Daniel
>
> >
> > > ---
> > > drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > index d602db2..b57f156 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -2518,8 +2518,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
> > > else
> > > hsw_shared_dplls_init(dev_priv);
> > >
> > > - DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
> > > - dev_priv->display.get_display_clock_speed(dev));
> > > + dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> > > + DRM_DEBUG_KMS("CDCLK running at %dKHz\n", dev_priv->cdclk_freq);
> > >
> > > if (IS_SKYLAKE(dev)) {
> > > if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> > > --
> > > 2.1.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-05-21 12:48 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-20 13:45 [PATCH 0/5] SKL S3, take 2.5 Damien Lespiau
2015-05-20 13:45 ` [PATCH 1/5] drm/i915/bxt: Also add bxt_resume_prepare() to the S3/S4 path Damien Lespiau
2015-05-20 13:45 ` [PATCH 2/5] drm/i915: Add a space after ', ' and don't capitalize mid-sentence Damien Lespiau
2015-05-20 13:45 ` [PATCH 3/5] drm/i915: Kill the dev variable in intel_suspend_complete() Damien Lespiau
2015-05-21 14:43 ` Ville Syrjälä
2015-05-20 13:45 ` [PATCH 4/5] drm/i915: Store boot CDCLK in dev_priv on DDI platforms Damien Lespiau
2015-05-20 15:53 ` Daniel Vetter
2015-05-20 15:56 ` Daniel Vetter
2015-05-21 12:48 ` Ville Syrjälä [this message]
2015-05-20 13:45 ` [PATCH 5/5] drm/i915/skl: Deinit/init the display at suspend/resume Damien Lespiau
2015-05-21 14:42 ` Ville Syrjälä
2015-05-21 15:37 ` [PATCH v3] " Damien Lespiau
2015-05-21 15:44 ` Ville Syrjälä
2015-05-21 15:49 ` Damien Lespiau
2015-05-21 15:58 ` Ville Syrjälä
2015-05-21 16:11 ` Damien Lespiau
2015-05-21 16:37 ` Ville Syrjälä
2015-05-21 15:54 ` Daniel Vetter
2015-05-22 5:52 ` shuang.he
2015-05-21 18:58 ` [PATCH 5/5] " shuang.he
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