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From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>,
	Daniel Vetter <daniel@ffwll.ch>,
	Michel Thierry <michel.thierry@intel.com>,
	intel-gfx@lists.freedesktop.org, akash.goel@intel.com
Subject: Re: [PATCH 15/16] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset
Date: Wed, 27 May 2015 14:02:30 +0200	[thread overview]
Message-ID: <20150527120230.GH8341@phenom.ffwll.local> (raw)
In-Reply-To: <20150526201611.GA1733@nuc-i3427.alporthouse.com>

On Tue, May 26, 2015 at 09:16:11PM +0100, Chris Wilson wrote:
> On Tue, May 26, 2015 at 05:25:48PM +0200, Daniel Vetter wrote:
> > On Tue, May 26, 2015 at 03:21:22PM +0100, Michel Thierry wrote:
> > > There are some allocations that must be only referenced by 32bit
> > > offsets.
> 
> > > To limit the chances of having the first 4GB already full,
> > > objects not requiring this workaround don't use the first 2 PDPs.
> 
> This is complete tosh. Please have a later patch that uses SEARCH_BELOW
> for 48bit objects, and cite eviction rates and improvements.

Yeah didn't spot that at first, I agree that trying to segregate objects
upfront is premature optimization. There's very few state objects
(compard to textures), usually of differen size classes and different
lifetimes. And they should all be reused anyway for efficient, so after a
few rounds of execbuf things should settle in nicely.

Let's avoid a bit of complexity here when not yet proven to be required.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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  reply	other threads:[~2015-05-27 12:00 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-26 14:21 [PATCH 00/16] 48b PPGTT Michel Thierry
2015-05-26 14:21 ` [PATCH 01/16] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-05-26 14:21 ` [PATCH 02/16] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-05-26 14:21 ` [PATCH 03/16] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-05-26 14:21 ` [PATCH 04/16] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-05-26 14:21 ` [PATCH 05/16] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-05-26 14:21 ` [PATCH 06/16] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-05-26 14:21 ` [PATCH 07/16] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-05-26 14:21 ` [PATCH 08/16] drm/i915: Plumb sg_iter through va allocation ->maps Michel Thierry
2015-05-26 14:21 ` [PATCH 09/16] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-05-26 15:10   ` Michel Thierry
2015-05-26 14:21 ` [PATCH 10/16] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-05-26 14:21 ` [PATCH 11/16] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-05-26 14:21 ` [PATCH 12/16] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-05-26 14:21 ` [PATCH 13/16] drm/i915: object size needs to be u64 Michel Thierry
2015-05-26 14:21 ` [PATCH 14/16] drm/i915: Check against correct user_size limit in 48b ppgtt mode Michel Thierry
2015-05-26 14:21 ` [PATCH 15/16] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-05-26 15:25   ` Daniel Vetter
2015-05-26 16:56     ` Michel Thierry
2015-05-26 20:16     ` Chris Wilson
2015-05-27 12:02       ` Daniel Vetter [this message]
2015-05-26 14:21 ` [PATCH 16/16] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-05-26 14:21 ` [PATCH] tests/gem_ppgtt: Check Wa32bitOffsets workarounds Michel Thierry

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