[PATCH 00/13] Update of the HDMI DPLL dividers computation

Damien Lespiau
2015-05-07T17:38:51Z

As explained in the important patch of this series:

The HW validation team came back from further testing with a slightly
changed constraint on the deviation between the DCO frequency and the
central frequency. Instead of +-4%, it's now +1%/-6%.

Unfortunately, the previous algorithm didn't quite cope with these new
constraints, the reason being that it wasn't thorough enough looking at
the possible divider candidates.

The new algorithm looks at all dividers, which is definitely a hammer
approach (we could reduce further the set of dividers to good ones as a
follow up, at the cost of a bit more complicated code). But, at least,
we can now satisfy the +1%/+6% rule for all the "Well known" HDMI
frequencies of my test set (373 entries).

tools/skl_compute_wrpll is what makes me a bit more confident that the code is
more correct than not. Which can help the review.

I found that we needed a full rewrite when testing a simpler solution based on
the current code: I couldn't light up one of the 1024x768 modes (65Mhz). Turned
out, the previous algorithm failed to respect the new constraints for:
6000000Hz, 39000000Hz, 57000000Hz, 61000000Hz, 65000000Hz, 65250000Hz,
65500000Hz, 66000000Hz, 71000000Hz, 72000000Hz, 76000000Hz. (From the list of
tested frequencies in the i-g-t test)

On top of this, I made a small refinement to the documented alrogithm to prefer
even dividers.

I believe it should be possible to retrain even further the list of potential
dividers we look at by choosing them around central_freq/afe_freq instead of
the full list of candidates, but it looks like it'd be more complicated code
for little gain.

--
Damien

Damien Lespiau (13):
drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()
drm/i915/skl: Make sure to break when not finding suitable PLL
dividers
drm/i915/skl: Display the WRPLL frequency we couldn't accomodate when
failing
drm/i915/skl: Propagate the error if we fail to find a suitable DPLL
divider
drm/i915/skl: Use a more idomatic early return
drm/i915/skl: Factor out computing the DPLL paramaters from the
dividers
drm/i915/skl: Remove unnecessary () used with div_u64()
drm/i915/skl: Remove unnecessary () used with abs_diff()
drm/i915/skl: Use MISSING_CASE() in skl_wrpll_params_populate()
drm/i915: Correctly prefix HSW/BDW HDMI clock functions
drm/i915/skl: Don't try to store the wrong central frequency
drm/i915/skl: Replace the HDMI DPLL divider computation algorithm
drm/i915/skl: Prefer even dividers for SKL DPLLs

drivers/gpu/drm/i915/intel_ddi.c | 366 ++++++++++++++++++++++++---------------
1 file changed, 223 insertions(+), 143 deletions(-)

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2.1.0