Re: [PATCH 13/13] drm/i915/skl: Prefer even dividers for SKL DPLLs

Paulo Zanoni
2015-05-27T21:39:40Z

2015-05-07 14:38 GMT-03:00 Damien Lespiau <damien.lespiau@intel.com>:
> Currently, if an odd divider improves the deviation (minimizes it), we
> take that divider. The recommendation is to prefer even dividers.

The doc says "It is preferred to get as close to the DCO central
frequency as possible, but using an even divider value takes
precedence.", but I'm wondering if they meant "prefer even over odd in
case they have the same deviation" or just "even divider is preferred
as long as it's on the deviation threshold, even if there's an odd
divider with minimal/no deviation". I see you implement the last
option - if you don't count the possible bug mentioned on my review of
patch 12.

Assuming the loop order will be fixed on patch 12, and assuming you
are correctly interpreting the spec, then your patch does what it
says, so: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>.

>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 381a8c9..54344c3 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1308,6 +1308,13 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> dco_freq,
> p);
> }
> +
> + /*
> + * If a solution is found with an even divider, prefer
> + * this one.
> + */
> + if (d == 0 && ctx.p)
> + break;
> }
> }
>
> --
> 2.1.0
>
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--
Paulo Zanoni