Re: [PATCH v4 02/12] drm/i915: Fix 852GM/GMV cdclk

[Damien Lespiau <damien.lespiau@intel.com>]

On Fri, May 22, 2015 at 11:22:32AM +0300, Mika Kahola wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> It seems 852GM/GMV uses a different HPLLCC encoding than the other
> 85x platforms. For 852GM/GMV cdclk is always 133MHz. Try to detect that
> using the PCI revision (sinc the device ID seems useless for that). I'm
> not at all sure this is a good idea, but according to the specs it
> should work.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> v2: Rebased to the latest
> v3: Rebased to the latest
> 
> Reviewed-by: Mika Kahola <mika.kahola@intel.com>

-ENODOC, FIXME and commit message -> not really inspiring.

Still, a probably better try then decoding HPLLCC.

Acked-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> Author:    Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 64debfb..4b17aad 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6631,6 +6631,14 @@ static int i85x_get_display_clock_speed(struct drm_device *dev)
>  {
>  	u16 hpllcc = 0;
>  
> +	/*
> +	 * 852GM/852GMV only supports 133 MHz and the HPLLCC
> +	 * encoding is different :(
> +	 * FIXME is this the right way to detect 852GM/852GMV?
> +	 */
> +	if (dev->pdev->revision == 0x1)
> +		return 133333;
> +
>  	pci_bus_read_config_word(dev->pdev->bus,
>  				 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
>  
> -- 
> 1.9.1
> 
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