Re: [PATCH 3/3] drm/i915/skl: Updated the i915_ring_freq_table debugfs function

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Jun 04, 2015 at 01:36:36PM +0530, Akash Goel wrote:
> On Wed, 2015-06-03 at 14:27 -0700, Rodrigo Vivi wrote:
> > On Tue, May 12, 2015 at 12:49 AM,  <akash.goel@intel.com> wrote:
> > > From: Akash Goel <akash.goel@intel.com>
> > >
> > > Updated the i915_ring_freq_table debugfs function to allow read of ring
> > > frequency table through Punit interface, for SKL also.
> > >
> > > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_debugfs.c | 21 ++++++++++++++++-----
> > >  1 file changed, 16 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 9e5a56c..32527de 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -1769,8 +1769,9 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> > >         struct drm_i915_private *dev_priv = dev->dev_private;
> > >         int ret = 0;
> > >         int gpu_freq, ia_freq;
> > > +       unsigned int max_gpu_freq, min_gpu_freq;
> > >
> > > -       if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
> > > +       if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_SKYLAKE(dev))) {
> > 
> > Why HSW and BDW aren't here and SKL is back?
> > Again, I'm without doc for this, sorry...
> 
> Sorry not sure that why HSW/BDW aren't used here. For them also this
> interface should work.

HSW is included in the GEN7 check. But so is VLV and that one should be
rejected. BDW is genuinely misising. Can you fix it all up while you're
poking at it?

> 
> > 
> > >                 seq_puts(m, "unsupported on this chipset\n");
> > >                 return 0;
> > >         }
> > > @@ -1783,17 +1784,27 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> > >         if (ret)
> > >                 goto out;
> > >
> > > +       if (IS_SKYLAKE(dev)) {
> > > +               /* Convert GT frequency to 50 HZ units */
> > > +               min_gpu_freq =
> > > +                       dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
> > > +               max_gpu_freq =
> > > +                       dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
> > > +       } else {
> > > +               min_gpu_freq = dev_priv->rps.min_freq_softlimit;
> > > +               max_gpu_freq = dev_priv->rps.max_freq_softlimit;
> > > +       }
> > > +
> > >         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
> > >
> > > -       for (gpu_freq = dev_priv->rps.min_freq_softlimit;
> > > -            gpu_freq <= dev_priv->rps.max_freq_softlimit;
> > > -            gpu_freq++) {
> > > +       for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
> > >                 ia_freq = gpu_freq;
> > >                 sandybridge_pcode_read(dev_priv,
> > >                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
> > >                                        &ia_freq);
> > >                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
> > > -                          intel_gpu_freq(dev_priv, gpu_freq),
> > > +                          intel_gpu_freq(dev_priv, (gpu_freq *
> > > +                               (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
> > 
> > here the scaler conversion made sense to me...
> > 
> > >                            ((ia_freq >> 0) & 0xff) * 100,
> > >                            ((ia_freq >> 8) & 0xff) * 100);
> > >         }
> > > --
> > > 1.9.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > 
> > 
> 
> 
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-- 
Ville Syrjälä
Intel OTC
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