[PATCH 1/7] drm/i915: Make broxton_set_cdclk() static

[PATCH 1/7] drm/i915: Make broxton_set_cdclk() static

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_drv.h     | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c38c297..a96f181 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5226,7 +5226,7 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
 	intel_display_set_init_power(dev_priv, false);
 }
 
-void broxton_set_cdclk(struct drm_device *dev, int frequency)
+static void broxton_set_cdclk(struct drm_device *dev, int frequency)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t divider;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cb3a30c..5312160 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1111,7 +1111,6 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void broxton_init_cdclk(struct drm_device *dev);
 void broxton_uninit_cdclk(struct drm_device *dev);
-void broxton_set_cdclk(struct drm_device *dev, int frequency);
 void broxton_ddi_phy_init(struct drm_device *dev);
 void broxton_ddi_phy_uninit(struct drm_device *dev);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
-- 
2.1.0

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[PATCH 2/7] drm/i915/skl: Derive the max CDCLK from DFSM

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  7 +++++++
 drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0f72c0e..cfe262c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5761,6 +5761,13 @@ enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT	0x46408
 #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
 
+#define SKL_DFSM			0x51000
+#define SKL_DFSM_CDCLK_LIMIT_MASK	(0x3 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_675	(  0 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_540	(  1 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_450	(  2 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_337_5	(  3 << 23)
+
 #define FF_SLICE_CS_CHICKEN2			0x20e4
 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a96f181..6989626 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5631,7 +5631,18 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (IS_BROADWELL(dev))  {
+	if (IS_SKYLAKE(dev)) {
+		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
+
+		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
+			dev_priv->max_cdclk_freq = 675000;
+		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
+			dev_priv->max_cdclk_freq = 540000;
+		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
+			dev_priv->max_cdclk_freq = 450000;
+		else
+			dev_priv->max_cdclk_freq = 337500;
+	} else if (IS_BROADWELL(dev))  {
 		/*
 		 * FIXME with extra cooling we can allow
 		 * 540 MHz for ULX and 675 Mhz for ULT.
-- 
2.1.0

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Re: [PATCH 2/7] drm/i915/skl: Derive the max CDCLK from DFSM

[Jani Nikula]

On Thu, 04 Jun 2015, Damien Lespiau <damien.lespiau@intel.com> wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  7 +++++++
>  drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++-
>  2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f72c0e..cfe262c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5761,6 +5761,13 @@ enum skl_disp_power_wells {
>  #define HSW_NDE_RSTWRN_OPT	0x46408
>  #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
>  
> +#define SKL_DFSM			0x51000
> +#define SKL_DFSM_CDCLK_LIMIT_MASK	(0x3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675	(  0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540	(  1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450	(  2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5	(  3 << 23)

Removed the spaces after ( while applying due to checkpatch whine.

BR,
Jani.


> +
>  #define FF_SLICE_CS_CHICKEN2			0x20e4
>  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a96f181..6989626 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5631,7 +5631,18 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	if (IS_BROADWELL(dev))  {
> +	if (IS_SKYLAKE(dev)) {
> +		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> +
> +		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
> +			dev_priv->max_cdclk_freq = 675000;
> +		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
> +			dev_priv->max_cdclk_freq = 540000;
> +		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
> +			dev_priv->max_cdclk_freq = 450000;
> +		else
> +			dev_priv->max_cdclk_freq = 337500;
> +	} else if (IS_BROADWELL(dev))  {
>  		/*
>  		 * FIXME with extra cooling we can allow
>  		 * 540 MHz for ULX and 675 Mhz for ULT.
> -- 
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH 3/7] drm/i915/skl: Don't warn if reading back DPLL0 is disabled

[Damien Lespiau]

We can operate with DPLL0 off with CDCLK backed by the 24Mhz reference
clock, and that's a supported configuration. Don't warn when notice
DPLL0 is off then.

We still have a separate warn at boot if cdclk is disabled (because we
don't currently try to handle the case (that shouldn't happen on SKL as
far as I know) where we boot with display not initialized.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6989626..d64f317 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6656,10 +6656,8 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
 	uint32_t cdctl = I915_READ(CDCLK_CTL);
 	uint32_t linkrate;
 
-	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
-		WARN(1, "LCPLL1 not enabled\n");
+	if (!(lcpll1 & LCPLL_PLL_ENABLE))
 		return 24000; /* 24MHz is the cd freq with NSSC ref */
-	}
 
 	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
 		return 540000;
-- 
2.1.0

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[PATCH 4/7] drm/i915: Don't display the boot CDCLK twice

[Damien Lespiau]

intel_update_cdclk() will already display the boot CDCLK for DDI
platforms, no need to repeat there.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3eaf5c0..fff4944 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2517,7 +2517,6 @@ void intel_ddi_pll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t val = I915_READ(LCPLL_CTL);
-	int cdclk_freq;
 
 	if (IS_SKYLAKE(dev))
 		skl_shared_dplls_init(dev_priv);
@@ -2526,10 +2525,10 @@ void intel_ddi_pll_init(struct drm_device *dev)
 	else
 		hsw_shared_dplls_init(dev_priv);
 
-	cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-	DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq);
-
 	if (IS_SKYLAKE(dev)) {
+		int cdclk_freq;
+
+		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
 		dev_priv->skl_boot_cdclk = cdclk_freq;
 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
 			DRM_ERROR("LCPLL1 is disabled\n");
-- 
2.1.0

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[PATCH 5/7] drm/i915/skl: Update the cached CDCLK at the end of set_cdclk()

[Damien Lespiau]

Ville's and Mika's cdclk series was in flight at the same time as the
SKL S3 patches so we were missing that update.

intel_update_max_cdclk() and intel_update_cdclk() had to be moved up a
bit to avoid forward declarations.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 137 ++++++++++++++++++-----------------
 1 file changed, 70 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d64f317..47c765d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5226,6 +5226,73 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
 	intel_display_set_init_power(dev_priv, false);
 }
 
+static void intel_update_max_cdclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (IS_SKYLAKE(dev)) {
+		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
+
+		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
+			dev_priv->max_cdclk_freq = 675000;
+		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
+			dev_priv->max_cdclk_freq = 540000;
+		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
+			dev_priv->max_cdclk_freq = 450000;
+		else
+			dev_priv->max_cdclk_freq = 337500;
+	} else if (IS_BROADWELL(dev))  {
+		/*
+		 * FIXME with extra cooling we can allow
+		 * 540 MHz for ULX and 675 Mhz for ULT.
+		 * How can we know if extra cooling is
+		 * available? PCI ID, VTB, something else?
+		 */
+		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
+			dev_priv->max_cdclk_freq = 450000;
+		else if (IS_BDW_ULX(dev))
+			dev_priv->max_cdclk_freq = 450000;
+		else if (IS_BDW_ULT(dev))
+			dev_priv->max_cdclk_freq = 540000;
+		else
+			dev_priv->max_cdclk_freq = 675000;
+	} else if (IS_VALLEYVIEW(dev)) {
+		dev_priv->max_cdclk_freq = 400000;
+	} else {
+		/* otherwise assume cdclk is fixed */
+		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
+	}
+
+	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
+			 dev_priv->max_cdclk_freq);
+}
+
+static void intel_update_cdclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
+	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
+			 dev_priv->cdclk_freq);
+
+	/*
+	 * Program the gmbus_freq based on the cdclk frequency.
+	 * BSpec erroneously claims we should aim for 4MHz, but
+	 * in fact 1MHz is the correct frequency.
+	 */
+	if (IS_VALLEYVIEW(dev)) {
+		/*
+		 * Program the gmbus_freq based on the cdclk frequency.
+		 * BSpec erroneously claims we should aim for 4MHz, but
+		 * in fact 1MHz is the correct frequency.
+		 */
+		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
+	}
+
+	if (dev_priv->max_cdclk_freq == 0)
+		intel_update_max_cdclk(dev);
+}
+
 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5517,6 +5584,7 @@ static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
 
 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
 {
+	struct drm_device *dev = dev_priv->dev;
 	u32 freq_select, pcu_ack;
 
 	DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
@@ -5557,6 +5625,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
 	mutex_lock(&dev_priv->rps.hw_lock);
 	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
 	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	intel_update_cdclk(dev);
 }
 
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
@@ -5627,73 +5697,6 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 	return vco_freq[hpll_freq] * 1000;
 }
 
-static void intel_update_max_cdclk(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (IS_SKYLAKE(dev)) {
-		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
-
-		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
-			dev_priv->max_cdclk_freq = 675000;
-		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
-			dev_priv->max_cdclk_freq = 540000;
-		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
-			dev_priv->max_cdclk_freq = 450000;
-		else
-			dev_priv->max_cdclk_freq = 337500;
-	} else if (IS_BROADWELL(dev))  {
-		/*
-		 * FIXME with extra cooling we can allow
-		 * 540 MHz for ULX and 675 Mhz for ULT.
-		 * How can we know if extra cooling is
-		 * available? PCI ID, VTB, something else?
-		 */
-		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
-			dev_priv->max_cdclk_freq = 450000;
-		else if (IS_BDW_ULX(dev))
-			dev_priv->max_cdclk_freq = 450000;
-		else if (IS_BDW_ULT(dev))
-			dev_priv->max_cdclk_freq = 540000;
-		else
-			dev_priv->max_cdclk_freq = 675000;
-	} else if (IS_VALLEYVIEW(dev)) {
-		dev_priv->max_cdclk_freq = 400000;
-	} else {
-		/* otherwise assume cdclk is fixed */
-		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
-	}
-
-	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
-			 dev_priv->max_cdclk_freq);
-}
-
-static void intel_update_cdclk(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
-			 dev_priv->cdclk_freq);
-
-	/*
-	 * Program the gmbus_freq based on the cdclk frequency.
-	 * BSpec erroneously claims we should aim for 4MHz, but
-	 * in fact 1MHz is the correct frequency.
-	 */
-	if (IS_VALLEYVIEW(dev)) {
-		/*
-		 * Program the gmbus_freq based on the cdclk frequency.
-		 * BSpec erroneously claims we should aim for 4MHz, but
-		 * in fact 1MHz is the correct frequency.
-		 */
-		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
-	}
-
-	if (dev_priv->max_cdclk_freq == 0)
-		intel_update_max_cdclk(dev);
-}
-
 /* Adjust CDclk dividers to allow high res or save power if possible */
 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 {
-- 
2.1.0

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[PATCH 6/7] drm/i915/bxt: Use intel_update_cdclk() to update dev_priv->cdclk_freq

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 47c765d..a232dc9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5409,7 +5409,7 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency)
 		return;
 	}
 
-	dev_priv->cdclk_freq = frequency;
+	intel_update_cdclk(dev);
 }
 
 void broxton_init_cdclk(struct drm_device *dev)
-- 
2.1.0

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[PATCH 7/7] drm/i915/skl: Warn if the cached cdclk freq is not the requested one

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a232dc9..a018465 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5627,6 +5627,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
 	intel_update_cdclk(dev);
+
+	WARN(freq != dev_priv->cdclk_freq,
+	     "cdclk requested %d kHz but got %d kHz\n",
+	     freq, dev_priv->cdclk_freq);
 }
 
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
-- 
2.1.0

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Re: [PATCH 7/7] drm/i915/skl: Warn if the cached cdclk freq is not the requested one

[Ville Syrjälä]

On Thu, Jun 04, 2015 at 06:21:35PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a232dc9..a018465 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5627,6 +5627,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
>  	mutex_unlock(&dev_priv->rps.hw_lock);
>  
>  	intel_update_cdclk(dev);
> +
> +	WARN(freq != dev_priv->cdclk_freq,
> +	     "cdclk requested %d kHz but got %d kHz\n",
> +	     freq, dev_priv->cdclk_freq);
>  }

Could you add this to all the set_cdclk() functions? Maybe
intel_check_cdclk() or something.

>  
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> -- 
> 2.1.0
> 
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-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 7/7] drm/i915/skl: Warn if the cached cdclk freq is not the requested one

[Damien Lespiau]

On Fri, Jun 05, 2015 at 03:24:45PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 04, 2015 at 06:21:35PM +0100, Damien Lespiau wrote:
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a232dc9..a018465 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5627,6 +5627,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
> >  	mutex_unlock(&dev_priv->rps.hw_lock);
> >  
> >  	intel_update_cdclk(dev);
> > +
> > +	WARN(freq != dev_priv->cdclk_freq,
> > +	     "cdclk requested %d kHz but got %d kHz\n",
> > +	     freq, dev_priv->cdclk_freq);
> >  }
> 
> Could you add this to all the set_cdclk() functions? Maybe
> intel_check_cdclk() or something.

I was thinking that we should probably introduce a low level
set_core_display_clock() vfunc and a intel_set_core_display_clock()
wrapper were we'd put the common code (updating the cached value, that
WARN(), ...)

Thoughts?

-- 
Damien
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Re: [PATCH 7/7] drm/i915/skl: Warn if the cached cdclk freq is not the requested one

[Ville Syrjälä]

On Fri, Jun 05, 2015 at 01:40:29PM +0100, Damien Lespiau wrote:
> On Fri, Jun 05, 2015 at 03:24:45PM +0300, Ville Syrjälä wrote:
> > On Thu, Jun 04, 2015 at 06:21:35PM +0100, Damien Lespiau wrote:
> > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index a232dc9..a018465 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5627,6 +5627,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
> > >  	mutex_unlock(&dev_priv->rps.hw_lock);
> > >  
> > >  	intel_update_cdclk(dev);
> > > +
> > > +	WARN(freq != dev_priv->cdclk_freq,
> > > +	     "cdclk requested %d kHz but got %d kHz\n",
> > > +	     freq, dev_priv->cdclk_freq);
> > >  }
> > 
> > Could you add this to all the set_cdclk() functions? Maybe
> > intel_check_cdclk() or something.
> 
> I was thinking that we should probably introduce a low level
> set_core_display_clock() vfunc and a intel_set_core_display_clock()
> wrapper were we'd put the common code (updating the cached value, that
> WARN(), ...)
> 
> Thoughts?

Yeah wrapper around the vfunc sounds better than sprinkling the same
stuff into every vfunc.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 7/7] drm/i915/skl: Warn if the cached cdclk freq is not the requested one

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6539
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  270/270              270/270
ILK                                  303/303              303/303
SNB                                  312/312              312/312
IVB                                  343/343              343/343
BYT                                  287/287              287/287
BDW                                  318/318              318/318
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 1/7] drm/i915: Make broxton_set_cdclk() static

[Ville Syrjälä]

On Thu, Jun 04, 2015 at 06:21:29PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

For patches 1-6
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_drv.h     | 1 -
>  2 files changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c38c297..a96f181 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5226,7 +5226,7 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
>  	intel_display_set_init_power(dev_priv, false);
>  }
>  
> -void broxton_set_cdclk(struct drm_device *dev, int frequency)
> +static void broxton_set_cdclk(struct drm_device *dev, int frequency)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t divider;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cb3a30c..5312160 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1111,7 +1111,6 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>  void broxton_init_cdclk(struct drm_device *dev);
>  void broxton_uninit_cdclk(struct drm_device *dev);
> -void broxton_set_cdclk(struct drm_device *dev, int frequency);
>  void broxton_ddi_phy_init(struct drm_device *dev);
>  void broxton_ddi_phy_uninit(struct drm_device *dev);
>  void bxt_enable_dc9(struct drm_i915_private *dev_priv);
> -- 
> 2.1.0
> 
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 1/7] drm/i915: Make broxton_set_cdclk() static

[Jani Nikula]

On Fri, 05 Jun 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Jun 04, 2015 at 06:21:29PM +0100, Damien Lespiau wrote:
>> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>
> For patches 1-6
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Said patches pushed to drm-intel-next-queued, thanks for the patches and
review.

BR,
Jani.



>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>>  drivers/gpu/drm/i915/intel_drv.h     | 1 -
>>  2 files changed, 1 insertion(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index c38c297..a96f181 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5226,7 +5226,7 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
>>  	intel_display_set_init_power(dev_priv, false);
>>  }
>>  
>> -void broxton_set_cdclk(struct drm_device *dev, int frequency)
>> +static void broxton_set_cdclk(struct drm_device *dev, int frequency)
>>  {
>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>>  	uint32_t divider;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index cb3a30c..5312160 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1111,7 +1111,6 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>>  void broxton_init_cdclk(struct drm_device *dev);
>>  void broxton_uninit_cdclk(struct drm_device *dev);
>> -void broxton_set_cdclk(struct drm_device *dev, int frequency);
>>  void broxton_ddi_phy_init(struct drm_device *dev);
>>  void broxton_ddi_phy_uninit(struct drm_device *dev);
>>  void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>> -- 
>> 2.1.0
>> 
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
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-- 
Jani Nikula, Intel Open Source Technology Center
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