Re: [PATCH v3 4/6] drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, Jun 05, 2015 at 02:56:48PM +0100, Arun Siluvery wrote:
> In Indirect context w/a batch buffer,
> +WaFlushCoherentL3CacheLinesAtContextSwitch
> 
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 1 +
>  drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84af255..5203c79 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -426,6 +426,7 @@
>  #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
>  #define   PIPE_CONTROL_NOTIFY				(1<<8)
>  #define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
> +#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
>  #define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
>  #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
>  #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index a71eb81..9d8cf65c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1101,6 +1101,14 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring)
>  	/* WaDisableCtxRestoreArbitration:bdw,chv */
>  	cmd[index++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
>  
> +	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw,chv */
> +	cmd[index++] = GFX_OP_PIPE_CONTROL(6);
> +	cmd[index++] = PIPE_CONTROL_DC_FLUSH_ENABLE;
> +	cmd[index++] = 0;
> +	cmd[index++] = 0;
> +	cmd[index++] = 0;
> +	cmd[index++] = 0;
> +

This looks incomplete. Seems like you should have LRIs around this
guy to enable/disable the L3SQCREG4 coherent line flush bit.

And chv shouldn't do coherent L3, so this might not be needed there.

Also do we need a CS stall here too?
"DC Flush Enable 5 Requires stall bit ([20] of DW) set for all GPGPU and Media Workloads."

Supposedly we should add the DC flush to the normal ring flush hooks
too. But that's a separate issue.

>  	/* padding */
>          while (index < end)
>  		cmd[index++] = MI_NOOP;
> -- 
> 2.3.0
> 
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-- 
Ville Syrjälä
Intel OTC
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