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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915: Actually respect DSPSURF alignment restrictions
Date: Fri, 12 Jun 2015 13:50:13 +0300	[thread overview]
Message-ID: <20150612105013.GX5176@intel.com> (raw)
In-Reply-To: <20150611135119.GF28462@nuc-i3427.alporthouse.com>

On Thu, Jun 11, 2015 at 02:51:19PM +0100, Chris Wilson wrote:
> On Thu, Jun 11, 2015 at 04:31:14PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently intel_gen4_compute_page_offset() simply picks the closest
> > page boundary below the linear offset. That however may not be suitably
> > aligned to satisfy any hardware specific restrictions. So let's make
> > sure the page boundary we choose is properly aligned.
> > 
> > Also to play it a bit safer lets split the remaining linear offset into
> > x and y values instead of just x. This should make no difference for
> > most platforms since we convert the x and y offsets back into a linear
> > offset before feeding them to the hardware. HSW+ are different however
> > and use x and y offsets even with linear buffers, so they might have
> > trouble if either the x or y get too big.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> 
> > @@ -2455,12 +2461,13 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y,
> >  
> >  		return tile_rows * pitch * 8 + tiles * 4096;
> >  	} else {
> > +		unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
> >  		unsigned int offset;
> >  
> >  		offset = *y * pitch + *x * cpp;
> > -		*y = 0;
> > -		*x = (offset & 4095) / cpp;
> > -		return offset & -4096;
> > +		*y = (offset & alignment) / pitch;
> > +		*x = ((offset & alignment) - *y * pitch) / cpp;
> > +		return offset & ~alignment;
> 
> Calculation looks solid. I presume we have a igt/kms test that combines
> linear/tiled, large surfaces and large offsets?

kms_plane has some kind of panning tests. Probably not as good as it
could/should be. I have a few custom tests I created to hunt for the
VLV/CHV bug, but those aren't really useable as regular igt tests as
is. Would take a bit of extra effort to turn them into such.

> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre

-- 
Ville Syrjälä
Intel OTC
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  reply	other threads:[~2015-06-12 10:50 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-11 13:31 [PATCH 1/3] drm/i915: Actually respect DSPSURF alignment restrictions ville.syrjala
2015-06-11 13:31 ` [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV ville.syrjala
2015-06-12  0:46   ` Clint Taylor
2015-06-12  4:47   ` Arun R Murthy
2015-06-11 13:31 ` [PATCH 3/3] drm/i915: Drop the 64k linear scanout alignment on gen2/3 ville.syrjala
2015-06-11 13:52   ` Chris Wilson
2015-06-14 23:18   ` shuang.he
2015-06-11 13:51 ` [PATCH 1/3] drm/i915: Actually respect DSPSURF alignment restrictions Chris Wilson
2015-06-12 10:50   ` Ville Syrjälä [this message]
2015-06-15 16:04     ` Daniel Vetter

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