From: Daniel Vetter <daniel@ffwll.ch>
To: Clint Taylor <clinton.a.taylor@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk
Date: Mon, 15 Jun 2015 12:26:44 +0200 [thread overview]
Message-ID: <20150615102644.GU8341@phenom.ffwll.local> (raw)
In-Reply-To: <557B07B8.4060107@intel.com>
On Fri, Jun 12, 2015 at 09:24:24AM -0700, Clint Taylor wrote:
> On 05/26/2015 10:22 AM, ville.syrjala@linux.intel.com wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Switch from using 31 PFI credits to 63 PFI credits when cdclk>=czclk on
> >CHV. The spec lists both 31 and 63 as "suggested" values, but based on
> >feedback from hardware folks we should actually be using 63. Originally
> >I picked the 31 basically by flipping a coin.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >index 067b1de..44b9c54 100644
> >--- a/drivers/gpu/drm/i915/intel_display.c
> >+++ b/drivers/gpu/drm/i915/intel_display.c
> >@@ -5986,7 +5986,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> > if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> > /* CHV suggested value is 31 or 63 */
> > if (IS_CHERRYVIEW(dev_priv))
> >- credits = PFI_CREDIT_31;
> >+ credits = PFI_CREDIT_63;
> > else
> > credits = PFI_CREDIT(15);
> > } else {
> >
>
> Although not part of this review the else clause is setting PFI_CREDIT to 15
> when the BPSEC states that the default of 8 should be used when cdclk/czclk
> < 1. According to the original patch, 15 is the optimal value as stated by
> another driver team.
Can you please file a bspec correction notice to fix the issue with the 15
vs. 8?
> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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prev parent reply other threads:[~2015-06-15 10:23 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-26 17:22 [PATCH 0/3] drm/i915: CHV DPIO and PFI stuff ville.syrjala
2015-05-26 17:22 ` [PATCH 1/3] drm/i915: Use the default 600ns LDO programming sequence delay ville.syrjala
2015-05-26 17:22 ` [PATCH 2/3] drm/i915: Throw out WIP CHV power well definitions ville.syrjala
2015-05-27 12:06 ` Daniel Vetter
2015-05-28 6:29 ` Ville Syrjälä
2015-05-26 17:22 ` [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk ville.syrjala
2015-06-12 16:24 ` Clint Taylor
2015-06-15 10:26 ` Daniel Vetter [this message]
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