From: Daniel Vetter <daniel@ffwll.ch>
To: Todd Previte <tprevite@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: Displayport compliance test 4.2.2.7 support
Date: Mon, 15 Jun 2015 17:39:47 +0200 [thread overview]
Message-ID: <20150615153947.GF8341@phenom.ffwll.local> (raw)
In-Reply-To: <1433895740-13698-3-git-send-email-tprevite@gmail.com>
On Tue, Jun 09, 2015 at 05:22:19PM -0700, Todd Previte wrote:
> Adds support for complying with the requirements for test 4.2.2.7 Branch
> Device Detection upon HPD Plug Event in the Displayport Link CTS 1.2 Core
> rev1.1. This test checks to see if the source device can properly detect
> a downstream branch device connected to the attached sink. It does so by
> advertising the presence of a downstream port through the DPCD. The sink
> count and content protection readiness bits are saved in the intel_dp
> struct.
>
> Note that as of HDCP 1.3 Displayport amendment, the CP_READY bit (bit 6)
> in the SINK_COUNT register (DPCD 0x200) is no longer used. This bit
> is stored here for compatibility for pre-HDCP 1.3 devices.
>
> V1:
> - Fixed formatting errors
> V2:
> - Updated for versioning
>
> Signed-off-by: Todd Previte <tprevite@gmail.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 12 +++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 4 ++++
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 14147d0..697857a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3856,8 +3856,18 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> intel_dp_print_rates(intel_dp);
>
> if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> - DP_DWN_STRM_PORT_PRESENT))
> + DP_DWN_STRM_PORT_PRESENT)) {
> return true; /* native DP sink */
> + } else {
> + uint8_t dpcd_byte;
> + /* Read Sink Count - DP Link CTS 1.2a rev1.1 4.2.2.7 */
> + intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
> + &dpcd_byte, 1);
> + intel_dp->sink_count = DP_GET_SINK_COUNT(dpcd_byte);
> + intel_dp->cp_ready = (dpcd_byte & DP_SINK_CP_READY) >> 6;
> + DRM_DEBUG_KMS("Sink count: %d CP: %02x\n",
> + intel_dp->sink_count, intel_dp->cp_ready);
> + }
>
> if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
> return true; /* no per-port downstream info */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6c71be9..f9a935c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -744,6 +744,10 @@ struct intel_dp {
> unsigned long compliance_test_type;
> unsigned long compliance_test_data;
> bool compliance_test_active;
> +
> + /* Branch device support */
> + uint8_t sink_count;
> + uint8_t cp_ready;
Isn't this something that the dp helpers already maintain? If so then we
should probably use that one. If not I wonder whether we shouldn't do
something with these sink values instead of just passing them around ...
-Daniel
> };
>
> struct intel_digital_port {
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2015-06-15 15:37 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-10 0:22 Add support for Displayport CTS 4.2.2.7, 4.2.2.8 and 4.2.2.9 Todd Previte
2015-06-10 0:22 ` [PATCH 1/3] drm/i915: Displayport compliance test 4.2.2.9 support Todd Previte
2015-06-15 15:37 ` Daniel Vetter
2015-06-15 15:50 ` Chris Wilson
2015-06-10 0:22 ` [PATCH 2/3] drm/i915: Displayport compliance test 4.2.2.7 support Todd Previte
2015-06-15 15:39 ` Daniel Vetter [this message]
2015-06-10 0:22 ` [PATCH 3/3] drm/i915: Displayport compliance test 4.2.2.8 support Todd Previte
2015-06-15 15:42 ` Daniel Vetter
2015-06-28 17:15 ` shuang.he
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