From: Daniel Vetter <daniel@ffwll.ch>
To: "Singh, Gaurav K" <gaurav.k.singh@intel.com>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [RFC 06/14] drm/i915: Disable vlank interrupt for disabling MIPI cmd mode
Date: Wed, 17 Jun 2015 13:36:22 +0200 [thread overview]
Message-ID: <20150617113622.GI23637@phenom.ffwll.local> (raw)
In-Reply-To: <558054E1.20602@intel.com>
On Tue, Jun 16, 2015 at 10:24:57PM +0530, Singh, Gaurav K wrote:
>
>
> On 5/29/2015 10:53 PM, Daniel Vetter wrote:
> >On Fri, May 29, 2015 at 07:14:43PM +0200, Daniel Vetter wrote:
> >>On Fri, May 29, 2015 at 04:06:58PM +0530, Gaurav K Singh wrote:
> >>>vblank interrupt should be disabled before starting the disable
> >>>sequence for MIPI command mode. Otherwise when pipe is disabled
> >>>TE interurpt will be still handled and one memory write command
> >>>will be sent with pipe disabled. This makes the pipe hw to get
> >>>stuck and it doesn't recover in the next enable sequence causing
> >>>display blank out.
> >>>
> >>>Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
> >>>Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> >>>---
> >>> drivers/gpu/drm/i915/intel_dsi.c | 14 ++++++++++++++
> >>> 1 file changed, 14 insertions(+)
> >>>
> >>>diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> >>>index 04d8ce0..aeea289 100644
> >>>--- a/drivers/gpu/drm/i915/intel_dsi.c
> >>>+++ b/drivers/gpu/drm/i915/intel_dsi.c
> >>>@@ -513,11 +513,25 @@ static void intel_dsi_enable_nop(struct intel_encoder *encoder)
> >>> static void intel_dsi_pre_disable(struct intel_encoder *encoder)
> >>> {
> >>>+ struct drm_device *dev = encoder->base.dev;
> >>> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> >>>+ struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> >>>+ int pipe = intel_crtc->pipe;
> >>> enum port port;
> >>> DRM_DEBUG_KMS("\n");
> >>>+ if (is_cmd_mode(intel_dsi)) {
> >>>+ dev->driver->disable_vblank(dev, pipe);
> >>>+
> >>>+ /*
> >>>+ * Make sure that the last frame is sent otherwise pipe can get
> >>>+ * stuck. Currently providing delay time for ~2 vblanks
> >>>+ * assuming 60fps.
> >>>+ */
> >>>+ mdelay(40);
> >>>+ }
> >>Nope. You need to move around the drm_vblank_off suitably, only that
> >>function correctly handles all the book-keeping around vblank interrupts.
> >>If this doesn't work out because of ordering we need to dig into this and
> >>figure out something. Worst case we need to push the drm_vblank_off call
> >>into encoder callbacks for everyone. That's something we already discussed
> >>but then decided against.
> >I seem to be blind, but where exactly is that vblank-driven upload code?
This question is still open for me. Why exactly do we have to disable
vblanks here already? I feel like this is hiding some deeper
synchronization issue - just disabling the vblank source doesn't mean they
have all be processed correctly by the irq handler. If this is really
required then you still have a big race here, even when using
drm_vblank_off.
-Daneil
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2015-06-17 11:33 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-29 10:36 [RFC 00/14] DSI Command mode(DBI mode) enabling on CHT Gaurav K Singh
2015-05-29 10:36 ` [RFC 01/14] drm/i915: allocate gem memory for mipi dbi cmd buffer Gaurav K Singh
2015-05-29 10:59 ` Ville Syrjälä
2015-05-29 17:10 ` Daniel Vetter
2015-06-01 11:03 ` Ville Syrjälä
2015-06-15 10:30 ` Daniel Vetter
2015-06-16 17:08 ` Singh, Gaurav K
2015-06-18 22:02 ` {Intel-gfx] " Gaurav K Singh
2015-06-18 22:06 ` Singh, Gaurav K
2015-05-29 10:36 ` [RFC 02/14] drm/i915: Add support for TEAR ON Sequence Gaurav K Singh
2015-05-29 10:36 ` [RFC 03/14] drm/i915: Add functions for dcs memory write cmd Gaurav K Singh
2015-05-29 10:36 ` [RFC 04/14] drm/i915: Calculate bw timer for mipi DBI interface Gaurav K Singh
2015-05-29 10:36 ` [RFC 05/14] drm/i915: Use the bpp value wrt the pixel format Gaurav K Singh
2015-05-29 10:36 ` [RFC 06/14] drm/i915: Disable vlank interrupt for disabling MIPI cmd mode Gaurav K Singh
2015-05-29 17:14 ` Daniel Vetter
2015-05-29 17:23 ` Daniel Vetter
2015-06-16 16:54 ` Singh, Gaurav K
2015-06-17 11:36 ` Daniel Vetter [this message]
2015-06-18 21:49 ` Gaurav K Singh
2015-06-22 11:58 ` Daniel Vetter
2015-05-29 10:36 ` [RFC 07/14] drm/i915: Disable MIPI display self refresh mode Gaurav K Singh
2015-05-29 17:16 ` Daniel Vetter
2015-05-29 17:20 ` Daniel Vetter
2015-06-16 16:59 ` Singh, Gaurav K
2015-06-18 21:53 ` Gaurav K Singh
2015-06-22 12:04 ` Daniel Vetter
2015-05-29 10:37 ` [RFC 08/14] drm/i915: Disable Tearing effect trigger by GPIO pin Gaurav K Singh
2015-05-29 10:37 ` [RFC 09/14] drm/i915: Changes for command mode preparation Gaurav K Singh
2015-05-29 10:37 ` [RFC 10/14] drm/i915: Enable Tearing effect trigger by GPIO pin Gaurav K Singh
2015-05-29 10:37 ` [RFC 11/14] drm/i915: Enable MIPI display self refresh mode Gaurav K Singh
2015-05-29 17:21 ` Daniel Vetter
2015-06-13 6:54 ` Mohan Marimuthu, Yogesh
2015-06-15 10:33 ` Daniel Vetter
2015-06-16 17:03 ` Singh, Gaurav K
2015-06-17 11:39 ` Daniel Vetter
2015-06-18 21:56 ` Gaurav K Singh
2015-06-22 12:05 ` Daniel Vetter
2015-06-22 12:08 ` Daniel Vetter
2015-05-29 10:37 ` [RFC 12/14] drm/i915: Generalize DSI enable function Gaurav K Singh
2015-05-29 10:37 ` [RFC 13/14] drm/i915: Reset the display hw if vid mode to cmd mode Gaurav K Singh
2015-05-29 10:37 ` [RFC 14/14] drm/i915: send one frame after enabling mipi " Gaurav K Singh
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