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From: Daniel Vetter <daniel@ffwll.ch>
To: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>,
	intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [RFC 07/14] drm/i915: Disable MIPI display self refresh mode
Date: Mon, 22 Jun 2015 14:04:30 +0200	[thread overview]
Message-ID: <20150622120430.GP25769@phenom.ffwll.local> (raw)
In-Reply-To: <1434664409-20380-1-git-send-email-gaurav.k.singh@intel.com>

On Fri, Jun 19, 2015 at 03:23:29AM +0530, Gaurav K Singh wrote:
> During disable sequence for MIPI encoder in command mode, disable
> MIPI display self-refresh mode bit in Pipe Ctrl reg.
> 
> v2: Use crtc state flag instead of loop over encoders (Daniel)
> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    3 +++
>  drivers/gpu/drm/i915/intel_drv.h     |    3 +++
>  drivers/gpu/drm/i915/intel_dsi.c     |    3 +++
>  3 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 067b1de..dd518d6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2193,6 +2193,9 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
>  	if ((val & PIPECONF_ENABLE) == 0)
>  		return;
>  
> +	if (crtc->config->dsi_self_refresh)
> +		val = val & ~PIPECONF_MIPI_DSR_ENABLE;

This shouldn't be required since we just clear all of PIPECONF when
disabling (well when re-enabling too) the crtc.

What's missing though is the hw state readout & cross-check support for
this new state bit. Also the code to set this bit seems to be missing.
-Daniel

> +
>  	/*
>  	 * Double wide has implications for planes
>  	 * so best keep it disabled when not needed.
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 14562c6..4298a00 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -444,6 +444,9 @@ struct intel_crtc_state {
>  	bool double_wide;
>  
>  	bool dp_encoder_is_mst;
> +
> +	bool dsi_self_refresh;
> +
>  	int pbn;
>  
>  	struct intel_crtc_scaler_state scaler_state;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 7021591..36d8ad6 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -308,6 +308,9 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>  
>  	DRM_DEBUG_KMS("\n");
>  
> +	if (is_cmd_mode(intel_dsi))
> +		config->dsi_self_refresh = true;
> +
>  	if (fixed_mode)
>  		intel_fixed_panel_mode(fixed_mode, adjusted_mode);
>  
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-06-22 12:01 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-29 10:36 [RFC 00/14] DSI Command mode(DBI mode) enabling on CHT Gaurav K Singh
2015-05-29 10:36 ` [RFC 01/14] drm/i915: allocate gem memory for mipi dbi cmd buffer Gaurav K Singh
2015-05-29 10:59   ` Ville Syrjälä
2015-05-29 17:10     ` Daniel Vetter
2015-06-01 11:03       ` Ville Syrjälä
2015-06-15 10:30         ` Daniel Vetter
2015-06-16 17:08           ` Singh, Gaurav K
2015-06-18 22:02             ` {Intel-gfx] " Gaurav K Singh
2015-06-18 22:06               ` Singh, Gaurav K
2015-05-29 10:36 ` [RFC 02/14] drm/i915: Add support for TEAR ON Sequence Gaurav K Singh
2015-05-29 10:36 ` [RFC 03/14] drm/i915: Add functions for dcs memory write cmd Gaurav K Singh
2015-05-29 10:36 ` [RFC 04/14] drm/i915: Calculate bw timer for mipi DBI interface Gaurav K Singh
2015-05-29 10:36 ` [RFC 05/14] drm/i915: Use the bpp value wrt the pixel format Gaurav K Singh
2015-05-29 10:36 ` [RFC 06/14] drm/i915: Disable vlank interrupt for disabling MIPI cmd mode Gaurav K Singh
2015-05-29 17:14   ` Daniel Vetter
2015-05-29 17:23     ` Daniel Vetter
2015-06-16 16:54       ` Singh, Gaurav K
2015-06-17 11:36         ` Daniel Vetter
2015-06-18 21:49         ` Gaurav K Singh
2015-06-22 11:58           ` Daniel Vetter
2015-05-29 10:36 ` [RFC 07/14] drm/i915: Disable MIPI display self refresh mode Gaurav K Singh
2015-05-29 17:16   ` Daniel Vetter
2015-05-29 17:20     ` Daniel Vetter
2015-06-16 16:59       ` Singh, Gaurav K
2015-06-18 21:53         ` Gaurav K Singh
2015-06-22 12:04           ` Daniel Vetter [this message]
2015-05-29 10:37 ` [RFC 08/14] drm/i915: Disable Tearing effect trigger by GPIO pin Gaurav K Singh
2015-05-29 10:37 ` [RFC 09/14] drm/i915: Changes for command mode preparation Gaurav K Singh
2015-05-29 10:37 ` [RFC 10/14] drm/i915: Enable Tearing effect trigger by GPIO pin Gaurav K Singh
2015-05-29 10:37 ` [RFC 11/14] drm/i915: Enable MIPI display self refresh mode Gaurav K Singh
2015-05-29 17:21   ` Daniel Vetter
2015-06-13  6:54     ` Mohan Marimuthu, Yogesh
2015-06-15 10:33       ` Daniel Vetter
2015-06-16 17:03         ` Singh, Gaurav K
2015-06-17 11:39           ` Daniel Vetter
2015-06-18 21:56           ` Gaurav K Singh
2015-06-22 12:05             ` Daniel Vetter
2015-06-22 12:08               ` Daniel Vetter
2015-05-29 10:37 ` [RFC 12/14] drm/i915: Generalize DSI enable function Gaurav K Singh
2015-05-29 10:37 ` [RFC 13/14] drm/i915: Reset the display hw if vid mode to cmd mode Gaurav K Singh
2015-05-29 10:37 ` [RFC 14/14] drm/i915: send one frame after enabling mipi " Gaurav K Singh

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