From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/5] drm/i915/vlv: factor out vlv_calc_port_clock
Date: Mon, 22 Jun 2015 16:33:11 +0300 [thread overview]
Message-ID: <20150622133311.GT5176@intel.com> (raw)
In-Reply-To: <1434637557-4856-4-git-send-email-imre.deak@intel.com>
On Thu, Jun 18, 2015 at 05:25:56PM +0300, Imre Deak wrote:
> This functionality will be needed by the next patch adding HW readout
> support for DDI ports on BXT, so factor it out.
>
> No functional change.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++--------
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0e5c613..6cf2a15 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7993,6 +7993,14 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
> I915_READ(LVDS) & LVDS_BORDER_ENABLE;
> }
>
> +int vlv_calc_port_clock(int refclk, intel_clock_t *pll_clock)
It doesn't work for VLV, so the name is misleading.
> +{
> + chv_clock(refclk, pll_clock);
> +
> + /* clock.dot is the fast clock */
> + return pll_clock->dot / 5;
> +}
Maybe just make chv_clock() return the divided down clock directtly
instead of adding this extra wrapper.
Though in that case I'd prefer if you change all the vlv_clock(),
i9xx_clock()... functions to do the same, just to keep the code
as similar as possible between platforms.
> +
> static void vlv_crtc_clock_get(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> @@ -8017,10 +8025,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
> clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
> clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
>
> - vlv_clock(refclk, &clock);
> -
> - /* clock.dot is the fast clock */
> - pipe_config->port_clock = clock.dot / 5;
> + pipe_config->port_clock = vlv_calc_port_clock(refclk, &clock);
> }
>
> static void
> @@ -8116,10 +8121,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
> clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
>
> - chv_clock(refclk, &clock);
> -
> - /* clock.dot is the fast clock */
> - pipe_config->port_clock = clock.dot / 5;
> + pipe_config->port_clock = vlv_calc_port_clock(refclk, &clock);
> }
>
> static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index bcafefc..95e14bb 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1139,6 +1139,8 @@ ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
> int dotclock);
> bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
> intel_clock_t *best_clock);
> +int vlv_calc_port_clock(int refclk, intel_clock_t *pll_clock);
> +
> bool intel_crtc_active(struct drm_crtc *crtc);
> void hsw_enable_ips(struct intel_crtc *crtc);
> void hsw_disable_ips(struct intel_crtc *crtc);
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-06-22 13:33 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-18 14:25 [PATCH 1/5] drm/i915/bxt: mask off the DPLL state checker bits we don't program Imre Deak
2015-06-18 14:25 ` [PATCH 2/5] drm/i915/bxt: add missing DDI PLL registers to the state checking Imre Deak
2015-06-24 10:07 ` Jindal, Sonika
2015-06-24 10:19 ` Imre Deak
2015-06-24 10:39 ` Daniel Vetter
2015-06-24 10:39 ` Jindal, Sonika
2015-06-18 14:25 ` [PATCH 3/5] drm/i915/bxt: add PLL10 to the PLL state dumper Imre Deak
2015-06-24 10:40 ` Jindal, Sonika
2015-06-18 14:25 ` [PATCH 4/5] drm/i915/vlv: factor out vlv_calc_port_clock Imre Deak
2015-06-22 13:33 ` Ville Syrjälä [this message]
2015-06-22 13:52 ` Imre Deak
2015-06-22 20:35 ` [PATCH v2 4/5] drm/i915/vlv: move the vlv PLL helper next to its platform counterparts Imre Deak
2015-06-30 3:13 ` Jindal, Sonika
2015-06-22 20:35 ` [PATCH v2 4.1/5] drm/i915: calculate the port clock rate along with other PLL params Imre Deak
2015-06-24 12:53 ` Ville Syrjälä
2015-06-30 9:56 ` Daniel Vetter
2015-06-24 10:16 ` [PATCH 4/5] drm/i915/vlv: factor out vlv_calc_port_clock Jindal, Sonika
2015-06-24 10:20 ` Imre Deak
2015-06-18 14:25 ` [PATCH 5/5] drm/i915/bxt: add DDI port HW readout support Imre Deak
2015-06-22 13:44 ` Ville Syrjälä
2015-06-22 14:22 ` Imre Deak
2015-06-22 14:40 ` Ville Syrjälä
2015-06-22 20:35 ` [PATCH v2 " Imre Deak
2015-06-24 10:40 ` [PATCH 1/5] drm/i915/bxt: mask off the DPLL state checker bits we don't program Jindal, Sonika
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150622133311.GT5176@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=imre.deak@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox