[PATCH 0/6] A bit of debug info for DMC/CSR

[PATCH 0/6] A bit of debug info for DMC/CSR

[Damien Lespiau]

We're flying a bit blind, so add some debug information about the DMC firmware.

# cat /sys/kernel/debug/dri/0/i915_dmc_info 
status: loaded
version: 1.18
DC5 allowed: no
DC6 allowed: yes
DC9 allowed: no
DC3 -> DC5 count: 0
DC5 -> DC6 count: 0
-- 
Damien

Damien Lespiau (6):
  drm/i915/skl: Print the DMC firmware status in debugfs
  drm/i915/skl: Store and print the DMC firmware version we load
  drm/i915/skl: Expose DC5/DC6 entry counts
  drm/i915/skl: Embed the CSR lock into its own structure
  drm/i915/skl: Print out if we allow DC5/DC6 in debugfs
  drm/i915/bxt: Print out if we allow DC9 in debugfs

 drivers/gpu/drm/i915/i915_debugfs.c     | 42 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_dma.c         |  1 -
 drivers/gpu/drm/i915/i915_drv.h         | 11 ++++++---
 drivers/gpu/drm/i915/i915_reg.h         |  4 ++++
 drivers/gpu/drm/i915/intel_csr.c        | 22 +++++++++++------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 30 +++++++++++++++++++++++
 6 files changed, 99 insertions(+), 11 deletions(-)

-- 
2.1.0

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[PATCH 1/6] drm/i915/skl: Print the DMC firmware status in debugfs

[Damien Lespiau]

Create a new debufs file for it, we'll have a few more things to add
there.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 31d8768..df35448 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2598,6 +2598,27 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_dmc_info(struct seq_file *m, void *unused)
+{
+
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	static const char *csr_state_str[] = { "unknown", "loaded", "error" };
+	enum csr_state csr_state;
+
+
+	if (!HAS_CSR(dev)) {
+		seq_puts(m, "not supported\n");
+		return 0;
+	}
+
+	csr_state = intel_csr_load_status_get(dev_priv);
+	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
+
+	return 0;
+}
+
 static void intel_seq_print_mode(struct seq_file *m, int tabs,
 				 struct drm_display_mode *mode)
 {
@@ -5068,6 +5089,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_energy_uJ", i915_energy_uJ, 0},
 	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
 	{"i915_power_domain_info", i915_power_domain_info, 0},
+	{"i915_dmc_info", i915_dmc_info, 0},
 	{"i915_display_info", i915_display_info, 0},
 	{"i915_semaphore_status", i915_semaphore_status, 0},
 	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
-- 
2.1.0

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[PATCH 2/6] drm/i915/skl: Store and print the DMC firmware version we load

[Damien Lespiau]

That can be handy later on to tell which DMC firmware version the user
has, by just looking at the dmesg or a debugfs file.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
 drivers/gpu/drm/i915/i915_drv.h     | 5 +++++
 drivers/gpu/drm/i915/intel_csr.c    | 8 +++++++-
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index df35448..5dad2ac 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2604,6 +2604,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	struct drm_info_node *node = m->private;
 	struct drm_device *dev = node->minor->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_csr *csr = &dev_priv->csr;
 	static const char *csr_state_str[] = { "unknown", "loaded", "error" };
 	enum csr_state csr_state;
 
@@ -2616,6 +2617,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	csr_state = intel_csr_load_status_get(dev_priv);
 	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
 
+	if (csr_state != FW_LOADED)
+		return 0;
+
+	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
+		   CSR_VERSION_MINOR(csr->version));
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 051298e..e15cb56 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -730,6 +730,10 @@ struct intel_uncore {
 #define for_each_fw_domain(domain__, dev_priv__, i__) \
 	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
 
+#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
+#define CSR_VERSION_MAJOR(version)	((version) >> 16)
+#define CSR_VERSION_MINOR(version)	((version) & 0xffff)
+
 enum csr_state {
 	FW_UNINITIALIZED = 0,
 	FW_LOADED,
@@ -740,6 +744,7 @@ struct intel_csr {
 	const char *fw_path;
 	__be32 *dmc_payload;
 	uint32_t dmc_fw_size;
+	uint32_t version;
 	uint32_t mmio_count;
 	uint32_t mmioaddr[8];
 	uint32_t mmiodata[8];
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 6d8a7bf..f83a2bf 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -300,6 +300,9 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 			(css_header->header_len * 4));
 		goto out;
 	}
+
+	csr->version = css_header->version;
+
 	readcount += sizeof(struct intel_css_header);
 
 	/* Extract Package Header information*/
@@ -389,7 +392,10 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	intel_csr_load_program(dev);
 	fw_loaded = true;
 
-	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
+	DRM_DEBUG_KMS("Finished loading %s (v%d.%d)\n", dev_priv->csr.fw_path,
+		      CSR_VERSION_MAJOR(csr->version),
+		      CSR_VERSION_MINOR(csr->version));
+
 out:
 	if (fw_loaded)
 		intel_runtime_pm_put(dev_priv);
-- 
2.1.0

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[PATCH 3/6] drm/i915/skl: Expose DC5/DC6 entry counts

[Damien Lespiau]

The CSR firmware expose two counters, handy to check if we are indeed
entering DC5/DC6.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
 drivers/gpu/drm/i915/i915_reg.h     | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5dad2ac..0af19c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2623,6 +2623,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
+	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
+		seq_printf(m, "DC3 -> DC5 count: %d\n",
+			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
+		seq_printf(m, "DC5 -> DC6 count: %d\n",
+			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac985c5..48a398c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5552,6 +5552,10 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_12BIT	(2 << 0)
 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
+/* DMC/CSR */
+#define SKL_CSR_DC3_DC5_COUNT	0x80030
+#define SKL_CSR_DC5_DC6_COUNT	0x8002C
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.1.0

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[PATCH 4/6] drm/i915/skl: Embed the CSR lock into its own structure

[Damien Lespiau]

When we have a well defined structure, it's customary to put the lock
protecting its fields inside.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c  |  1 -
 drivers/gpu/drm/i915/i915_drv.h  |  5 ++---
 drivers/gpu/drm/i915/intel_csr.c | 14 ++++++++------
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c5349fa..1ebf0e1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -820,7 +820,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	spin_lock_init(&dev_priv->mmio_flip_lock);
 	mutex_init(&dev_priv->sb_lock);
 	mutex_init(&dev_priv->modeset_restore_lock);
-	mutex_init(&dev_priv->csr_lock);
 
 	intel_pm_setup(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e15cb56..64c5184 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -741,6 +741,8 @@ enum csr_state {
 };
 
 struct intel_csr {
+	struct mutex lock;
+
 	const char *fw_path;
 	__be32 *dmc_payload;
 	uint32_t dmc_fw_size;
@@ -1689,9 +1691,6 @@ struct drm_i915_private {
 
 	struct intel_csr csr;
 
-	/* Display CSR-related protection */
-	struct mutex csr_lock;
-
 	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 
 	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index f83a2bf..d51cbae 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -211,9 +211,9 @@ enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
 {
 	enum csr_state state;
 
-	mutex_lock(&dev_priv->csr_lock);
+	mutex_lock(&dev_priv->csr.lock);
 	state = dev_priv->csr.state;
-	mutex_unlock(&dev_priv->csr_lock);
+	mutex_unlock(&dev_priv->csr.lock);
 
 	return state;
 }
@@ -228,9 +228,9 @@ enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
 			enum csr_state state)
 {
-	mutex_lock(&dev_priv->csr_lock);
+	mutex_lock(&dev_priv->csr.lock);
 	dev_priv->csr.state = state;
-	mutex_unlock(&dev_priv->csr_lock);
+	mutex_unlock(&dev_priv->csr.lock);
 }
 
 /**
@@ -252,7 +252,7 @@ void intel_csr_load_program(struct drm_device *dev)
 		return;
 	}
 
-	mutex_lock(&dev_priv->csr_lock);
+	mutex_lock(&dev_priv->csr.lock);
 	fw_size = dev_priv->csr.dmc_fw_size;
 	for (i = 0; i < fw_size; i++)
 		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
@@ -264,7 +264,7 @@ void intel_csr_load_program(struct drm_device *dev)
 	}
 
 	dev_priv->csr.state = FW_LOADED;
-	mutex_unlock(&dev_priv->csr_lock);
+	mutex_unlock(&dev_priv->csr.lock);
 }
 
 static void finish_csr_load(const struct firmware *fw, void *context)
@@ -429,6 +429,8 @@ void intel_csr_ucode_init(struct drm_device *dev)
 		return;
 	}
 
+	mutex_init(&dev_priv->csr.lock);
+
 	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 
 	/*
-- 
2.1.0

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[PATCH 5/6] drm/i915/skl: Print out if we allow DC5/DC6 in debugfs

[Damien Lespiau]

Instead of following the traces, it's easier to just look at a debugfs
file to figure out if the driver is allowing the CSR to go into DC
states.

We cache that information into the CSR structure as we don't want to
read registers in D3 (for instance).

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     |  5 +++++
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++++++++++++++
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0af19c0..878cc7f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2623,6 +2623,11 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
+	mutex_lock(&csr->lock);
+	seq_printf(m, "DC5 allowed: %s\n", yesno(csr->dc5_allowed));
+	seq_printf(m, "DC6 allowed: %s\n", yesno(csr->dc6_allowed));
+	mutex_unlock(&csr->lock);
+
 	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
 		seq_printf(m, "DC3 -> DC5 count: %d\n",
 			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 64c5184..99a09dd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -751,6 +751,7 @@ struct intel_csr {
 	uint32_t mmioaddr[8];
 	uint32_t mmiodata[8];
 	enum csr_state state;
+	bool dc5_allowed, dc6_allowed;
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e021b1a..bfcc990 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -491,6 +491,7 @@ static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 
 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	assert_can_enable_dc5(dev_priv);
@@ -504,10 +505,15 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 	val |= DC_STATE_EN_UPTO_DC5;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc5_allowed = true;
+	mutex_unlock(&csr->lock);
 }
 
 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	assert_can_disable_dc5(dev_priv);
@@ -518,6 +524,10 @@ static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 	val &= ~DC_STATE_EN_UPTO_DC5;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc5_allowed = false;
+	mutex_unlock(&csr->lock);
 }
 
 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
@@ -550,6 +560,7 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 
 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	assert_can_enable_dc6(dev_priv);
@@ -563,10 +574,15 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 	val |= DC_STATE_EN_UPTO_DC6;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc6_allowed = true;
+	mutex_unlock(&csr->lock);
 }
 
 static void skl_disable_dc6(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	if (intel_csr_load_status_get(dev_priv) != FW_LOADED)
@@ -580,6 +596,10 @@ static void skl_disable_dc6(struct drm_i915_private *dev_priv)
 	val &= ~DC_STATE_EN_UPTO_DC6;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc6_allowed = false;
+	mutex_unlock(&csr->lock);
 }
 
 static void skl_set_power_well(struct drm_i915_private *dev_priv,
-- 
2.1.0

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[PATCH 6/6] drm/i915/bxt: Print out if we allow DC9 in debugfs

[Damien Lespiau]

Just like the DC5/DC6 states on SKL, but this time for BXT's DC9.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     |  1 +
 drivers/gpu/drm/i915/i915_drv.h         |  2 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 878cc7f..0bc8b37 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2626,6 +2626,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	mutex_lock(&csr->lock);
 	seq_printf(m, "DC5 allowed: %s\n", yesno(csr->dc5_allowed));
 	seq_printf(m, "DC6 allowed: %s\n", yesno(csr->dc6_allowed));
+	seq_printf(m, "DC9 allowed: %s\n", yesno(csr->dc9_allowed));
 	mutex_unlock(&csr->lock);
 
 	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 99a09dd..129e148 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -751,7 +751,7 @@ struct intel_csr {
 	uint32_t mmioaddr[8];
 	uint32_t mmiodata[8];
 	enum csr_state state;
-	bool dc5_allowed, dc6_allowed;
+	bool dc5_allowed, dc6_allowed, dc9_allowed;
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index bfcc990..31f003a4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -415,6 +415,7 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 
 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	assert_can_enable_dc9(dev_priv);
@@ -425,10 +426,15 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 	val |= DC_STATE_EN_DC9;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc9_allowed = true;
+	mutex_unlock(&csr->lock);
 }
 
 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 {
+	struct intel_csr *csr = &dev_priv->csr;
 	uint32_t val;
 
 	assert_can_disable_dc9(dev_priv);
@@ -439,6 +445,10 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 	val &= ~DC_STATE_EN_DC9;
 	I915_WRITE(DC_STATE_EN, val);
 	POSTING_READ(DC_STATE_EN);
+
+	mutex_lock(&csr->lock);
+	csr->dc9_allowed = false;
+	mutex_unlock(&csr->lock);
 }
 
 static void gen9_set_dc_state_debugmask_memory_up(
-- 
2.1.0

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Re: [PATCH 1/6] drm/i915/skl: Print the DMC firmware status in debugfs

[Daniel Vetter]

On Tue, Jun 30, 2015 at 07:28:54PM +0100, Damien Lespiau wrote:
> Create a new debufs file for it, we'll have a few more things to add
> there.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 31d8768..df35448 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2598,6 +2598,27 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
>  	return 0;
>  }
>  
> +static int i915_dmc_info(struct seq_file *m, void *unused)
> +{
> +
> +	struct drm_info_node *node = m->private;
> +	struct drm_device *dev = node->minor->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	static const char *csr_state_str[] = { "unknown", "loaded", "error" };
> +	enum csr_state csr_state;
> +
> +
> +	if (!HAS_CSR(dev)) {
> +		seq_puts(m, "not supported\n");
> +		return 0;
> +	}
> +
> +	csr_state = intel_csr_load_status_get(dev_priv);

This will disappear after the dmc loader rework.
-Daniel

> +	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
> +
> +	return 0;
> +}
> +
>  static void intel_seq_print_mode(struct seq_file *m, int tabs,
>  				 struct drm_display_mode *mode)
>  {
> @@ -5068,6 +5089,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
>  	{"i915_energy_uJ", i915_energy_uJ, 0},
>  	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
>  	{"i915_power_domain_info", i915_power_domain_info, 0},
> +	{"i915_dmc_info", i915_dmc_info, 0},
>  	{"i915_display_info", i915_display_info, 0},
>  	{"i915_semaphore_status", i915_semaphore_status, 0},
>  	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 4/6] drm/i915/skl: Embed the CSR lock into its own structure

[Daniel Vetter]

On Tue, Jun 30, 2015 at 07:28:57PM +0100, Damien Lespiau wrote:
> When we have a well defined structure, it's customary to put the lock
> protecting its fields inside.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c  |  1 -
>  drivers/gpu/drm/i915/i915_drv.h  |  5 ++---
>  drivers/gpu/drm/i915/intel_csr.c | 14 ++++++++------
>  3 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index c5349fa..1ebf0e1 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -820,7 +820,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  	spin_lock_init(&dev_priv->mmio_flip_lock);
>  	mutex_init(&dev_priv->sb_lock);
>  	mutex_init(&dev_priv->modeset_restore_lock);
> -	mutex_init(&dev_priv->csr_lock);
>  
>  	intel_pm_setup(dev);
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e15cb56..64c5184 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -741,6 +741,8 @@ enum csr_state {
>  };
>  
>  struct intel_csr {
> +	struct mutex lock;

There wont be a lock left after the dmc loader rework.
-Daniel

> +
>  	const char *fw_path;
>  	__be32 *dmc_payload;
>  	uint32_t dmc_fw_size;
> @@ -1689,9 +1691,6 @@ struct drm_i915_private {
>  
>  	struct intel_csr csr;
>  
> -	/* Display CSR-related protection */
> -	struct mutex csr_lock;
> -
>  	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
>  
>  	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index f83a2bf..d51cbae 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -211,9 +211,9 @@ enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
>  {
>  	enum csr_state state;
>  
> -	mutex_lock(&dev_priv->csr_lock);
> +	mutex_lock(&dev_priv->csr.lock);
>  	state = dev_priv->csr.state;
> -	mutex_unlock(&dev_priv->csr_lock);
> +	mutex_unlock(&dev_priv->csr.lock);
>  
>  	return state;
>  }
> @@ -228,9 +228,9 @@ enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
>  void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
>  			enum csr_state state)
>  {
> -	mutex_lock(&dev_priv->csr_lock);
> +	mutex_lock(&dev_priv->csr.lock);
>  	dev_priv->csr.state = state;
> -	mutex_unlock(&dev_priv->csr_lock);
> +	mutex_unlock(&dev_priv->csr.lock);
>  }
>  
>  /**
> @@ -252,7 +252,7 @@ void intel_csr_load_program(struct drm_device *dev)
>  		return;
>  	}
>  
> -	mutex_lock(&dev_priv->csr_lock);
> +	mutex_lock(&dev_priv->csr.lock);
>  	fw_size = dev_priv->csr.dmc_fw_size;
>  	for (i = 0; i < fw_size; i++)
>  		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
> @@ -264,7 +264,7 @@ void intel_csr_load_program(struct drm_device *dev)
>  	}
>  
>  	dev_priv->csr.state = FW_LOADED;
> -	mutex_unlock(&dev_priv->csr_lock);
> +	mutex_unlock(&dev_priv->csr.lock);
>  }
>  
>  static void finish_csr_load(const struct firmware *fw, void *context)
> @@ -429,6 +429,8 @@ void intel_csr_ucode_init(struct drm_device *dev)
>  		return;
>  	}
>  
> +	mutex_init(&dev_priv->csr.lock);
> +
>  	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
>  
>  	/*
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 1/6] drm/i915/skl: Print the DMC firmware status in debugfs

[Damien Lespiau]

On Wed, Jul 01, 2015 at 03:16:24PM +0200, Daniel Vetter wrote:
> On Tue, Jun 30, 2015 at 07:28:54PM +0100, Damien Lespiau wrote:
> > Create a new debufs file for it, we'll have a few more things to add
> > there.
> > 
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 31d8768..df35448 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2598,6 +2598,27 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
> >  	return 0;
> >  }
> >  
> > +static int i915_dmc_info(struct seq_file *m, void *unused)
> > +{
> > +
> > +	struct drm_info_node *node = m->private;
> > +	struct drm_device *dev = node->minor->dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	static const char *csr_state_str[] = { "unknown", "loaded", "error" };
> > +	enum csr_state csr_state;
> > +
> > +
> > +	if (!HAS_CSR(dev)) {
> > +		seq_puts(m, "not supported\n");
> > +		return 0;
> > +	}
> > +
> > +	csr_state = intel_csr_load_status_get(dev_priv);
> 
> This will disappear after the dmc loader rework.

Are you suggesting that we shouldn't touch that code until someone
reworks it? (seems fairly unbounded to me).

-- 
Damien
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