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From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Daniel Vetter <daniel.vetter@intel.com>
Subject: Re: [PATCH] drm/i915: RMW register cycles considered evil
Date: Mon, 6 Jul 2015 23:35:06 +0200	[thread overview]
Message-ID: <20150706213506.GP7568@phenom.ffwll.local> (raw)
In-Reply-To: <CA+gsUGRndEUvqQbcUg34D9-R_mKU4Xqz6TeStSKx5SCC1jcJWQ@mail.gmail.com>

On Mon, Jul 06, 2015 at 04:23:23PM -0300, Paulo Zanoni wrote:
> 2015-07-06 12:04 GMT-03:00 Daniel Vetter <daniel@ffwll.ch>:
> > On Mon, Jul 06, 2015 at 03:50:49PM +0300, Ville Syrjälä wrote:
> >> On Mon, Jul 06, 2015 at 02:42:02PM +0200, Daniel Vetter wrote:
> >> > Especially for workarounds which is stuff that's almost impossible to
> >> > verify: The initial state from the firmware on boot-up and after
> >> > resume could be different, which will hide bugs when we do an RMW
> >> > cycle.
> >>
> >> If you're really worried about that then we should then explicitly
> >> initialize all the registers that might affect stuff.
> >>
> >> For a bunch of GT registers we could just do a GPU reset at driver
> >> init. That that won't help with UCGCTL and such.
> >>
> >> I'm also worried that if we don't use RMWs for early parts, the hardware
> >> folks may still change the default for some ofhte other bits, and then
> >> we end up clobbering those.
> >
> > The point is that we'll at least consistently clobber them, which is the
> > important part. Chasing a bug which only happens when you freshly boot but
> > not after the first gpu reset (or first resume or the other way round or
> > whatever) is not fun at all.
> 
> I think there are possibly other ways to be consistent. We could, for
> example, save the values which we think are correct at boot - even if
> we rely on the BIOS - and then (optionally) check them at every resume
> or runtime resume. Maybe there are even other ideas for that.
> 
> But I do see the value in what you're doing, even though I'm also
> afraid of the possible bugs brought by it, and I like the idea of
> starting this with new gens only. If you decide to keep this strategy,
> can you please print on debugfs when the RMW value is different from
> the non-RMW value?

We have a few testcases somewhere which try to make sure the w/a stick
after the usual suspects. Unfortunately the kernel instrumentation is very
weak for that (atm it only covers the render ring init w/a we do). We
could try to extend that a bit.

Or we could start screaming into dmesg if the rmw has an effect, like
you're suggesting.
-Daneil
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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  reply	other threads:[~2015-07-06 21:32 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-06 12:42 [PATCH] drm/i915: RMW register cycles considered evil Daniel Vetter
2015-07-06 12:46 ` Damien Lespiau
2015-07-06 14:58   ` Daniel Vetter
2015-07-06 15:15     ` Damien Lespiau
2015-07-06 18:32       ` Daniel Vetter
2015-07-06 12:50 ` Ville Syrjälä
2015-07-06 14:07   ` Dave Gordon
2015-07-06 15:00     ` Daniel Vetter
2015-07-06 15:04   ` Daniel Vetter
2015-07-06 19:23     ` Paulo Zanoni
2015-07-06 21:35       ` Daniel Vetter [this message]
2015-07-07 14:24 ` shuang.he

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