From: Daniel Vetter <daniel@ffwll.ch>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Check idle to active before processing CSQ
Date: Fri, 7 Aug 2015 13:52:22 +0200 [thread overview]
Message-ID: <20150807115222.GL17734@phenom.ffwll.local> (raw)
In-Reply-To: <871tffy0n7.fsf@gaia.fi.intel.com>
On Fri, Aug 07, 2015 at 11:15:56AM +0300, Mika Kuoppala wrote:
> Daniel Vetter <daniel@ffwll.ch> writes:
>
> > On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
> >> If idle to active bit is set, the rest of the fields
> >> in CSQ are not valid.
> >>
> >> Bail out early if this is the case in order to prevent
> >> rest of the loop inspecting stale values.
> >>
> >> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> >
> > Same questions here too, what's the impact. E.g. if you only found this by
> > bspec/code inspection then it's for -next, but if it's to fix some known
> > breakage then it's for -fixes + cc: stable.
> >
>
> To this and the masked write one: Both of these were found
> when I was trying to find out root cause for skl hangs.
>
> They are both for -next. Both are in the correctness
> department vrt bspec and I haven't observed any other
> impact.
>
> Point taken on being more verbose.
Thanks I added a note about this to the first patch and merged it. This
one here still seems to miss an r-b.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2015-08-07 11:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-06 14:09 [PATCH] drm/i915: Check idle to active before processing CSQ Mika Kuoppala
2015-08-06 16:04 ` Daniel Vetter
2015-08-07 8:15 ` Mika Kuoppala
2015-08-07 11:52 ` Daniel Vetter [this message]
2015-08-07 14:30 ` Siluvery, Arun
2015-08-11 10:01 ` Daniel Vetter
2015-08-12 20:52 ` shuang.he
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