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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp
Date: Wed, 12 Aug 2015 19:04:22 +0300	[thread overview]
Message-ID: <20150812160422.GB5176@intel.com> (raw)
In-Reply-To: <1436184606-18729-1-git-send-email-ville.syrjala@linux.intel.com>

On Mon, Jul 06, 2015 at 03:09:59PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> While working on CHV DPIO powergating I relized DP .compute_config() was
> clobbering lane_count etc. stored in intel_dp. This could cause problems
> if we do the .compute_config() but later fail the modeset for some reason.
> Any subsequent link re-training might then fail if intel_dp->lane_count
> etc. got changed.
> 
> The reason I ran into this during the DPIO powergating work was that I may
> need to know which lanes he active when shutting down the link. However
> .compute_config() already clobbered that information by the time I need it.
> By moving it to the pipe config we avoid that problem as well.
> 
> I also cleaned up the limited color range handling a bit while I was
> in the neighborhood.
> 

>   drm/i915: Clean up DP/HDMI limited color range handling
>   drm/i915: Move intel_dp->lane_count into pipe_config

These two are still lacking a r-b. Would be nice to get these in so that
they don't end up blocking the CHV DPIO powergating stuff once that gets
reviewed.

Sivakumar, any chance you'd like to review those as well? Or do we have
anyone else interested?

-- 
Ville Syrjälä
Intel OTC
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  parent reply	other threads:[~2015-08-12 16:04 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-06 12:09 [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp ville.syrjala
2015-07-06 12:10 ` [PATCH 1/7] drm/i915: Clean up DP/HDMI limited color range handling ville.syrjala
2015-08-13  6:16   ` Sivakumar Thulasimani
2015-08-13 12:01     ` Ville Syrjälä
2015-07-06 12:10 ` [PATCH 2/7] drm/i915: Don't use link_bw for PLL setup ville.syrjala
2015-07-07  8:05   ` Sivakumar Thulasimani
2015-08-11 17:21   ` [PATCH v2 " ville.syrjala
2015-07-06 12:10 ` [PATCH 3/7] drm/i915: Don't pass clock to DDI PLL select functions ville.syrjala
2015-07-07  8:07   ` Sivakumar Thulasimani
2015-07-06 12:10 ` [PATCH 4/7] drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config() ville.syrjala
2015-07-07  8:14   ` Sivakumar Thulasimani
2015-07-06 12:10 ` [PATCH 5/7] drm/i915: Move intel_dp->lane_count into pipe_config ville.syrjala
2015-07-06 13:39   ` [PATCH v2 " ville.syrjala
2015-08-13  7:00     ` Sivakumar Thulasimani
2015-07-06 12:10 ` [PATCH 6/7] drm/i915: Don't use link_bw to select between TP1 and TP3 ville.syrjala
2015-07-07  8:18   ` Sivakumar Thulasimani
2015-07-06 12:10 ` [PATCH 7/7] drm/i915: Kill intel_dp->{link_bw, rate_select} ville.syrjala
2015-07-07  8:46   ` Sivakumar Thulasimani
2015-07-10 23:13   ` shuang.he
2015-08-12 16:04 ` Ville Syrjälä [this message]
2015-08-14  8:23   ` [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp Daniel Vetter
2015-08-17  8:42 ` Maarten Lankhorst
2015-08-17 12:03   ` Ville Syrjälä
2015-08-25 12:57     ` Daniel Vetter
2015-08-25 14:11       ` Ville Syrjälä

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