[PATCH v3 00/11] Check pixel clock when setting mode

[PATCH v3 00/11] Check pixel clock when setting mode

[Mika Kahola]

From EDID we can read and request higher pixel clock than
our HW can support. This set of patches add checks if
requested pixel clock is lower than the one supported by the HW.
The requested mode is discarded if we cannot support the requested
pixel clock. For example for Cherryview

'cvt 2560 1600 60' gives

# 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync

where pixel clock 348.50 MHz is higher than the supported 304 MHz.

The checks are implemented for DisplayPort, HDMI, LVDS, DVO, SDVO, DSI,
CRT, TV, and DP-MST.

V2:
- The maximum DOT clock frequency is added to debugfs i915_frequency_info.
- max dotclock cached in dev_priv structure
- moved computation of max dotclock to 'intel_display.c'

V3:
- intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
- for GEN9 and above the max dotclock frequency is equal to CD clock
  frequency
- for older generations the dot clock frequency is limited to 90% of the
  CD clock frequency
- For Cherryview the dot clock is limited to 95% of CD clock frequency
- for GEN2/3 the maximum dot clock frequency is limited to 90% of the
  2X CD clock frequency as we have on option to use double wide mode
- cleanup

Mika Kahola (11):
  drm/i915: Store max dotclock
  drm/i915: DisplayPort pixel clock check
  drm/i915: HDMI pixel clock check
  drm/i915: LVDS pixel clock check
  drm/i915: SDVO pixel clock check
  drm/i915: DSI pixel clock check
  drm/i915: CRT pixel clock check
  drm/i915: TV pixel clock check
  drm/i915: DisplayPort-MST pixel clock check
  drm/i915: DVO pixel clock check
  drm/i915: Max DOT clock frequency to debugfs

 drivers/gpu/drm/i915/i915_debugfs.c  |  2 ++
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_crt.c     |  4 ++++
 drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c      |  3 ++-
 drivers/gpu/drm/i915/intel_dp_mst.c  |  5 +++++
 drivers/gpu/drm/i915/intel_dsi.c     |  4 ++++
 drivers/gpu/drm/i915/intel_dvo.c     |  4 ++++
 drivers/gpu/drm/i915/intel_hdmi.c    |  4 ++++
 drivers/gpu/drm/i915/intel_lvds.c    |  3 +++
 drivers/gpu/drm/i915/intel_sdvo.c    |  4 ++++
 drivers/gpu/drm/i915/intel_tv.c      |  4 ++++
 12 files changed, 56 insertions(+), 1 deletion(-)

-- 
1.9.1

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[PATCH v3 01/11] drm/i915: Store max dotclock

[Mika Kahola]

Store max dotclock into dev_priv structure so we are able
to filter out the modes that are not supported by our
platforms.

V2:
- limit the max dot clock frequency to max CD clock frequency
  for the gen9 and above
- limit the max dot clock frequency to 90% of the max CD clock
  frequency for the older gens
- for Cherryview the max dot clock frequency is limited to 95%
  of the max CD clock frequency
- for gen2 and gen3 the max dot clock limit is set to 90% of the
  2X max CD clock frequency

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04aa34a..1f69211b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1777,6 +1777,7 @@ struct drm_i915_private {
 	unsigned int fsb_freq, mem_freq, is_ddr3;
 	unsigned int skl_boot_cdclk;
 	unsigned int cdclk_freq, max_cdclk_freq;
+	unsigned int max_dotclk;
 	unsigned int hpll_freq;
 
 	/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 43b0f17..c9c6d19 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5259,6 +5259,23 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
 			modeset_put_power_domains(dev_priv, put_domains[i]);
 }
 
+static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
+{
+	int max_cdclk_freq = dev_priv->max_cdclk_freq;
+	int max_dotclk_freq;
+
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		max_dotclk_freq = max_cdclk_freq;
+	else if (IS_CHERRYVIEW(dev_priv))
+		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 95, 100);
+	else if (INTEL_INFO(dev_priv)->gen == 2 || INTEL_INFO(dev_priv)->gen == 3)
+		max_dotclk_freq = DIV_ROUND_UP(2 * max_cdclk_freq * 90, 100);
+	else
+		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 90, 100);
+
+	return max_dotclk_freq;
+}
+
 static void intel_update_max_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5298,6 +5315,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
 	}
 
+	dev_priv->max_dotclk = intel_compute_max_dotclk(dev_priv);
+
 	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
 			 dev_priv->max_cdclk_freq);
 }
-- 
1.9.1

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Re: [PATCH v3 01/11] drm/i915: Store max dotclock

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:50PM +0300, Mika Kahola wrote:
> Store max dotclock into dev_priv structure so we are able
> to filter out the modes that are not supported by our
> platforms.
> 
> V2:
> - limit the max dot clock frequency to max CD clock frequency
>   for the gen9 and above
> - limit the max dot clock frequency to 90% of the max CD clock
>   frequency for the older gens
> - for Cherryview the max dot clock frequency is limited to 95%
>   of the max CD clock frequency
> - for gen2 and gen3 the max dot clock limit is set to 90% of the
>   2X max CD clock frequency
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 04aa34a..1f69211b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1777,6 +1777,7 @@ struct drm_i915_private {
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
>  	unsigned int skl_boot_cdclk;
>  	unsigned int cdclk_freq, max_cdclk_freq;
> +	unsigned int max_dotclk;

nit: maybe max_dotclk_freq for extra consistentcy?

>  	unsigned int hpll_freq;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 43b0f17..c9c6d19 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5259,6 +5259,23 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
>  			modeset_put_power_domains(dev_priv, put_domains[i]);
>  }
>  
> +static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> +{
> +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> +	int max_dotclk_freq;
> +
> +	if (INTEL_INFO(dev_priv)->gen >= 9)
> +		max_dotclk_freq = max_cdclk_freq;
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 95, 100);
> +	else if (INTEL_INFO(dev_priv)->gen == 2 || INTEL_INFO(dev_priv)->gen == 3)

intel_crtc_compute_config() uses 'gen < 4' as the condition around the
double_wide handling. Maybe do the same here for consistency.

> +		max_dotclk_freq = DIV_ROUND_UP(2 * max_cdclk_freq * 90, 100);
> +	else
> +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 90, 100);

These should round down to match what we do in the calc_cdclk funcs.

Also to add another bikeshed color, there's no need for the local
max_dotclk_freq variable, you can just 'return <whatever>' from each
branch.

With at least the rounding fixed this can have
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
> +	return max_dotclk_freq;
> +}
> +
>  static void intel_update_max_cdclk(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5298,6 +5315,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>  		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
>  	}
>  
> +	dev_priv->max_dotclk = intel_compute_max_dotclk(dev_priv);
> +
>  	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
>  			 dev_priv->max_cdclk_freq);
>  }
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v3 01/11] drm/i915: Store max dotclock

[Ville Syrjälä]

On Wed, Aug 12, 2015 at 08:30:23PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 31, 2015 at 03:13:50PM +0300, Mika Kahola wrote:
> > Store max dotclock into dev_priv structure so we are able
> > to filter out the modes that are not supported by our
> > platforms.
> > 
> > V2:
> > - limit the max dot clock frequency to max CD clock frequency
> >   for the gen9 and above
> > - limit the max dot clock frequency to 90% of the max CD clock
> >   frequency for the older gens
> > - for Cherryview the max dot clock frequency is limited to 95%
> >   of the max CD clock frequency
> > - for gen2 and gen3 the max dot clock limit is set to 90% of the
> >   2X max CD clock frequency
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  1 +
> >  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
> >  2 files changed, 20 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 04aa34a..1f69211b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1777,6 +1777,7 @@ struct drm_i915_private {
> >  	unsigned int fsb_freq, mem_freq, is_ddr3;
> >  	unsigned int skl_boot_cdclk;
> >  	unsigned int cdclk_freq, max_cdclk_freq;
> > +	unsigned int max_dotclk;
> 
> nit: maybe max_dotclk_freq for extra consistentcy?
> 
> >  	unsigned int hpll_freq;
> >  
> >  	/**
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 43b0f17..c9c6d19 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5259,6 +5259,23 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
> >  			modeset_put_power_domains(dev_priv, put_domains[i]);
> >  }
> >  
> > +static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > +{
> > +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > +	int max_dotclk_freq;
> > +
> > +	if (INTEL_INFO(dev_priv)->gen >= 9)
> > +		max_dotclk_freq = max_cdclk_freq;
> > +	else if (IS_CHERRYVIEW(dev_priv))
> > +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 95, 100);
> > +	else if (INTEL_INFO(dev_priv)->gen == 2 || INTEL_INFO(dev_priv)->gen == 3)
> 
> intel_crtc_compute_config() uses 'gen < 4' as the condition around the
> double_wide handling. Maybe do the same here for consistency.
> 
> > +		max_dotclk_freq = DIV_ROUND_UP(2 * max_cdclk_freq * 90, 100);
> > +	else
> > +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 90, 100);
> 
> These should round down to match what we do in the calc_cdclk funcs.
> 
> Also to add another bikeshed color, there's no need for the local
> max_dotclk_freq variable, you can just 'return <whatever>' from each
> branch.
> 
> With at least the rounding fixed this can have
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > +
> > +	return max_dotclk_freq;
> > +}
> > +
> >  static void intel_update_max_cdclk(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -5298,6 +5315,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> >  		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
> >  	}
> >  
> > +	dev_priv->max_dotclk = intel_compute_max_dotclk(dev_priv);
> > +
> >  	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
> >  			 dev_priv->max_cdclk_freq);

Oh and I think it would be nice to add a DRM_DEBUG_DRIVER for the
compute max_dotclk so that we'll have it handy in bug reports without
having to recompute it in ones head.

> >  }
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v3 01/11] drm/i915: Store max dotclock

[Mika Kahola]

On Wed, 2015-08-12 at 22:01 +0300, Ville Syrjälä wrote:
> On Wed, Aug 12, 2015 at 08:30:23PM +0300, Ville Syrjälä wrote:
> > On Fri, Jul 31, 2015 at 03:13:50PM +0300, Mika Kahola wrote:
> > > Store max dotclock into dev_priv structure so we are able
> > > to filter out the modes that are not supported by our
> > > platforms.
> > > 
> > > V2:
> > > - limit the max dot clock frequency to max CD clock frequency
> > >   for the gen9 and above
> > > - limit the max dot clock frequency to 90% of the max CD clock
> > >   frequency for the older gens
> > > - for Cherryview the max dot clock frequency is limited to 95%
> > >   of the max CD clock frequency
> > > - for gen2 and gen3 the max dot clock limit is set to 90% of the
> > >   2X max CD clock frequency
> > > 
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h      |  1 +
> > >  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
> > >  2 files changed, 20 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 04aa34a..1f69211b 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1777,6 +1777,7 @@ struct drm_i915_private {
> > >  	unsigned int fsb_freq, mem_freq, is_ddr3;
> > >  	unsigned int skl_boot_cdclk;
> > >  	unsigned int cdclk_freq, max_cdclk_freq;
> > > +	unsigned int max_dotclk;
> > 
> > nit: maybe max_dotclk_freq for extra consistentcy?
> > 
> > >  	unsigned int hpll_freq;
> > >  
> > >  	/**
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 43b0f17..c9c6d19 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5259,6 +5259,23 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
> > >  			modeset_put_power_domains(dev_priv, put_domains[i]);
> > >  }
> > >  
> > > +static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > > +{
> > > +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > > +	int max_dotclk_freq;
> > > +
> > > +	if (INTEL_INFO(dev_priv)->gen >= 9)
> > > +		max_dotclk_freq = max_cdclk_freq;
> > > +	else if (IS_CHERRYVIEW(dev_priv))
> > > +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 95, 100);
> > > +	else if (INTEL_INFO(dev_priv)->gen == 2 || INTEL_INFO(dev_priv)->gen == 3)
> > 
> > intel_crtc_compute_config() uses 'gen < 4' as the condition around the
> > double_wide handling. Maybe do the same here for consistency.
> > 
> > > +		max_dotclk_freq = DIV_ROUND_UP(2 * max_cdclk_freq * 90, 100);
> > > +	else
> > > +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 90, 100);
> > 
> > These should round down to match what we do in the calc_cdclk funcs.
> > 
> > Also to add another bikeshed color, there's no need for the local
> > max_dotclk_freq variable, you can just 'return <whatever>' from each
> > branch.
> > 
> > With at least the rounding fixed this can have
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > > +
> > > +	return max_dotclk_freq;
> > > +}
> > > +
> > >  static void intel_update_max_cdclk(struct drm_device *dev)
> > >  {
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > @@ -5298,6 +5315,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> > >  		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
> > >  	}
> > >  
> > > +	dev_priv->max_dotclk = intel_compute_max_dotclk(dev_priv);
> > > +
> > >  	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
> > >  			 dev_priv->max_cdclk_freq);
> 
> Oh and I think it would be nice to add a DRM_DEBUG_DRIVER for the
> compute max_dotclk so that we'll have it handy in bug reports without
> having to recompute it in ones head.
> 
Thanks Ville for the review. I will work my way up towards v4 based on
your comments.

Cheers,
Mika

> > >  }
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> 


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[PATCH v3 02/11] drm/i915: DisplayPort pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DisplayPort.

V2:
- removed computation for max DOT clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 44f8a32..5faeadb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -206,6 +206,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
+	int max_pixclk = to_i915(connector->dev)->max_dotclk;
 
 	if (is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
@@ -223,7 +224,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);
 
-	if (mode_rate > max_rate)
+	if (mode_rate > max_rate || target_clock > max_pixclk)
 		return MODE_CLOCK_HIGH;
 
 	if (mode->clock < 10000)
-- 
1.9.1

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Re: [PATCH v3 02/11] drm/i915: DisplayPort pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:51PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DisplayPort.
> 
> V2:
> - removed computation for max DOT clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 44f8a32..5faeadb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -206,6 +206,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
>  	int target_clock = mode->clock;
>  	int max_rate, mode_rate, max_lanes, max_link_clock;
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
>  
>  	if (is_edp(intel_dp) && fixed_mode) {
>  		if (mode->hdisplay > fixed_mode->hdisplay)
> @@ -223,7 +224,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
>  	mode_rate = intel_dp_link_required(target_clock, 18);
>  
> -	if (mode_rate > max_rate)
> +	if (mode_rate > max_rate || target_clock > max_pixclk)
>  		return MODE_CLOCK_HIGH;

This one ends up checking the fixed_mode clock every time, but I think I
already declared that to OK, so let's go with it.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


>  	if (mode->clock < 10000)
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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[PATCH v3 03/11] drm/i915: HDMI pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to HDMI.

V2:
- removed computation for max dot clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 70bad5b..3149e5f 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1193,10 +1193,14 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 	enum drm_mode_status status;
 	int clock;
+	int max_pixclk = to_i915(connector->dev)->max_dotclk;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	clock = mode->clock;
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		clock *= 2;
-- 
1.9.1

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Re: [PATCH v3 03/11] drm/i915: HDMI pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:52PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to HDMI.
> 
> V2:
> - removed computation for max dot clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 70bad5b..3149e5f 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1193,10 +1193,14 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
>  	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
>  	enum drm_mode_status status;
>  	int clock;
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return MODE_NO_DBLESCAN;
>  
> +	if (mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;
> +
>  	clock = mode->clock;

I believe we should do something like this here:

	clock = mode->clock;

	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
		clock *= 2;

	if (clock > max_pixclk)
		return MODE_CLOCK_HIGH;

>  	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
>  		clock *= 2;

The stero handling should probably be in a separate patch, but in
preparation for it you could already put the dotclk check between the
clock= assigment and the DBCLK doubling (since DBLCLK only affects the
port_clock and not pixel clock).

> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Re: [PATCH v3 03/11] drm/i915: HDMI pixel clock check

[Daniel Vetter]

On Wed, Aug 12, 2015 at 09:34:54PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 31, 2015 at 03:13:52PM +0300, Mika Kahola wrote:
> > It is possible the we request to have a mode that has
> > higher pixel clock than our HW can support. This patch
> > checks if requested pixel clock is lower than the one
> > supported by the HW. The requested mode is discarded
> > if we cannot support the requested pixel clock.
> > 
> > This patch applies to HDMI.
> > 
> > V2:
> > - removed computation for max dot clock
> > 
> > V3:
> > - cleanup by removing unnecessary lines
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_hdmi.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 70bad5b..3149e5f 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1193,10 +1193,14 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> >  	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> >  	enum drm_mode_status status;
> >  	int clock;
> > +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
> >  
> >  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> >  		return MODE_NO_DBLESCAN;
> >  
> > +	if (mode->clock > max_pixclk)
> > +		return MODE_CLOCK_HIGH;
> > +
> >  	clock = mode->clock;
> 
> I believe we should do something like this here:
> 
> 	clock = mode->clock;
> 
> 	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
> 		clock *= 2;

That's already done in drm_mode_set_crtcinfo, i915 uses the STEREO_DOUBLE
mode of that function.
-Daniel

> 
> 	if (clock > max_pixclk)
> 		return MODE_CLOCK_HIGH;
> 
> >  	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> >  		clock *= 2;
> 
> The stero handling should probably be in a separate patch, but in
> preparation for it you could already put the dotclk check between the
> clock= assigment and the DBCLK doubling (since DBLCLK only affects the
> port_clock and not pixel clock).
> 
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Re: [PATCH v3 03/11] drm/i915: HDMI pixel clock check

[Ville Syrjälä]

On Fri, Aug 14, 2015 at 10:30:26AM +0200, Daniel Vetter wrote:
> On Wed, Aug 12, 2015 at 09:34:54PM +0300, Ville Syrjälä wrote:
> > On Fri, Jul 31, 2015 at 03:13:52PM +0300, Mika Kahola wrote:
> > > It is possible the we request to have a mode that has
> > > higher pixel clock than our HW can support. This patch
> > > checks if requested pixel clock is lower than the one
> > > supported by the HW. The requested mode is discarded
> > > if we cannot support the requested pixel clock.
> > > 
> > > This patch applies to HDMI.
> > > 
> > > V2:
> > > - removed computation for max dot clock
> > > 
> > > V3:
> > > - cleanup by removing unnecessary lines
> > > 
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_hdmi.c | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index 70bad5b..3149e5f 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -1193,10 +1193,14 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> > >  	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> > >  	enum drm_mode_status status;
> > >  	int clock;
> > > +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
> > >  
> > >  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> > >  		return MODE_NO_DBLESCAN;
> > >  
> > > +	if (mode->clock > max_pixclk)
> > > +		return MODE_CLOCK_HIGH;
> > > +
> > >  	clock = mode->clock;
> > 
> > I believe we should do something like this here:
> > 
> > 	clock = mode->clock;
> > 
> > 	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
> > 		clock *= 2;
> 
> That's already done in drm_mode_set_crtcinfo, i915 uses the STEREO_DOUBLE
> mode of that function.

Only for modesets. .mode_valid() only deals with the results of
.get_modes() etc., so the timings won't have been doubled. And even then
we only double the .crtc_ timings, which is where I previously gave up
trying to use the same mode validation code during modeset and .fill_modes().
I suppose we can make it happen if we really try, but in the meantime I
think it's at least an improvement if we stop advertising modes we for
sure can't use.

> -Daniel
> 
> > 
> > 	if (clock > max_pixclk)
> > 		return MODE_CLOCK_HIGH;
> > 
> > >  	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> > >  		clock *= 2;
> > 
> > The stero handling should probably be in a separate patch, but in
> > preparation for it you could already put the dotclk check between the
> > clock= assigment and the DBCLK doubling (since DBLCLK only affects the
> > port_clock and not pixel clock).
> > 
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v3 03/11] drm/i915: HDMI pixel clock check

[Daniel Vetter]

On Fri, Aug 14, 2015 at 04:03:55PM +0300, Ville Syrjälä wrote:
> On Fri, Aug 14, 2015 at 10:30:26AM +0200, Daniel Vetter wrote:
> > On Wed, Aug 12, 2015 at 09:34:54PM +0300, Ville Syrjälä wrote:
> > > On Fri, Jul 31, 2015 at 03:13:52PM +0300, Mika Kahola wrote:
> > > > It is possible the we request to have a mode that has
> > > > higher pixel clock than our HW can support. This patch
> > > > checks if requested pixel clock is lower than the one
> > > > supported by the HW. The requested mode is discarded
> > > > if we cannot support the requested pixel clock.
> > > > 
> > > > This patch applies to HDMI.
> > > > 
> > > > V2:
> > > > - removed computation for max dot clock
> > > > 
> > > > V3:
> > > > - cleanup by removing unnecessary lines
> > > > 
> > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_hdmi.c | 4 ++++
> > > >  1 file changed, 4 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > index 70bad5b..3149e5f 100644
> > > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > @@ -1193,10 +1193,14 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> > > >  	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> > > >  	enum drm_mode_status status;
> > > >  	int clock;
> > > > +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
> > > >  
> > > >  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> > > >  		return MODE_NO_DBLESCAN;
> > > >  
> > > > +	if (mode->clock > max_pixclk)
> > > > +		return MODE_CLOCK_HIGH;
> > > > +
> > > >  	clock = mode->clock;
> > > 
> > > I believe we should do something like this here:
> > > 
> > > 	clock = mode->clock;
> > > 
> > > 	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
> > > 		clock *= 2;
> > 
> > That's already done in drm_mode_set_crtcinfo, i915 uses the STEREO_DOUBLE
> > mode of that function.
> 
> Only for modesets. .mode_valid() only deals with the results of
> .get_modes() etc., so the timings won't have been doubled. And even then
> we only double the .crtc_ timings, which is where I previously gave up
> trying to use the same mode validation code during modeset and .fill_modes().
> I suppose we can make it happen if we really try, but in the meantime I
> think it's at least an improvement if we stop advertising modes we for
> sure can't use.

Oh right totally mixed things up, you're correct.
-Daniel

> 
> > -Daniel
> > 
> > > 
> > > 	if (clock > max_pixclk)
> > > 		return MODE_CLOCK_HIGH;
> > > 
> > > >  	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> > > >  		clock *= 2;
> > > 
> > > The stero handling should probably be in a separate patch, but in
> > > preparation for it you could already put the dotclk check between the
> > > clock= assigment and the DBCLK doubling (since DBLCLK only affects the
> > > port_clock and not pixel clock).
> > > 
> > > > -- 
> > > > 1.9.1
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel OTC
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 04/11] drm/i915: LVDS pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to LVDS.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_lvds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index cb634f4..59213f9 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -289,11 +289,14 @@ intel_lvds_mode_valid(struct drm_connector *connector,
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	int max_pixclk = to_i915(connector->dev)->max_dotclk;
 
 	if (mode->hdisplay > fixed_mode->hdisplay)
 		return MODE_PANEL;
 	if (mode->vdisplay > fixed_mode->vdisplay)
 		return MODE_PANEL;
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
 }
-- 
1.9.1

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Re: [PATCH v3 04/11] drm/i915: LVDS pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:53PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to LVDS.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lvds.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index cb634f4..59213f9 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -289,11 +289,14 @@ intel_lvds_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
>  
>  	if (mode->hdisplay > fixed_mode->hdisplay)
>  		return MODE_PANEL;
>  	if (mode->vdisplay > fixed_mode->vdisplay)
>  		return MODE_PANEL;
> +	if (mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;

This should really be checking fixed_mode->clock. Though checking it
every time is a bit pointless since it never changes. But what the eDP
cases ends up doing as well.

Maybe we should just stick the check to where we pick fixed_mode, or
perhaps just have intel_panel_init() print an error if the provided
modes(s) are no good? In theory that should never happen anyway.

>  
>  	return MODE_OK;
>  }
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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[PATCH v3 05/11] drm/i915: SDVO pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to SDVO.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 2c435a7..55a2853 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1560,6 +1560,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 		      struct drm_display_mode *mode)
 {
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
+	int max_pixclk = to_i915(connector->dev)->max_dotclk;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -1570,6 +1571,9 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 	if (intel_sdvo->pixel_clock_max < mode->clock)
 		return MODE_CLOCK_HIGH;
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	if (intel_sdvo->is_lvds) {
 		if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
 			return MODE_PANEL;
-- 
1.9.1

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Re: [PATCH v3 05/11] drm/i915: SDVO pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:54PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to SDVO.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sdvo.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 2c435a7..55a2853 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1560,6 +1560,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
>  		      struct drm_display_mode *mode)
>  {
>  	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return MODE_NO_DBLESCAN;
> @@ -1570,6 +1571,9 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
>  	if (intel_sdvo->pixel_clock_max < mode->clock)
>  		return MODE_CLOCK_HIGH;
>  
> +	if (mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;
> +

Had to think a bit on this one. But yeah checking mode->clock is the
right thing. I suppose in theory we should do the whole
intel_sdvo_get_preferred_input_mode() thing here, but I guess that would
clobber the current sdvo device state and so can't be done safely.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  	if (intel_sdvo->is_lvds) {
>  		if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
>  			return MODE_PANEL;
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH v3 06/11] drm/i915: DSI pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DSI.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 18dd7d7..3def6f9 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -654,6 +654,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	int max_pixclk = to_i915(connector->dev)->max_dotclk;
 
 	DRM_DEBUG_KMS("\n");
 
@@ -669,6 +670,9 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 			return MODE_PANEL;
 	}
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	return MODE_OK;
 }
 
-- 
1.9.1

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Re: [PATCH v3 06/11] drm/i915: DSI pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:55PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DSI.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 18dd7d7..3def6f9 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -654,6 +654,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
>  
>  	DRM_DEBUG_KMS("\n");
>  
> @@ -669,6 +670,9 @@ intel_dsi_mode_valid(struct drm_connector *connector,
>  			return MODE_PANEL;
>  	}
>  
> +	if (mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;
> +

Hmm. Seems like this too ought to be checking the fixed_mode.
intel_dsi_mode_valid() seems to assume there could be no fixed mode,
but looking at intel_dsi_init() tells me that can't be (if we ignore the
totally broken looking error handling).

Also we don't set up the panel fitter in the DSI code even though the
presence of fixed_mode clearly indicates that we should. So the whole
thing seems more or less busted.

For now, I think just sticking the clock check inside the 'if (fixed_mode)'
block would be fine, and then someone can try to clean up the bigger
mess.

>  	return MODE_OK;
>  }
>  
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH v3 07/11] drm/i915: CRT pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to CRT.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 5d78c1f..40ded5f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -290,6 +290,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct drm_device *dev = connector->dev;
+	int max_pixclk = to_i915(dev)->max_dotclk;
 
 	int max_clock = 0;
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -305,6 +306,9 @@ intel_crt_mode_valid(struct drm_connector *connector,
 	if (mode->clock > max_clock)
 		return MODE_CLOCK_HIGH;
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 	if (HAS_PCH_LPT(dev) &&
 	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
-- 
1.9.1

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Re: [PATCH v3 07/11] drm/i915: CRT pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:56PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to CRT.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_crt.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 5d78c1f..40ded5f 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -290,6 +290,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  		     struct drm_display_mode *mode)
>  {
>  	struct drm_device *dev = connector->dev;
> +	int max_pixclk = to_i915(dev)->max_dotclk;
>  
>  	int max_clock = 0;
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> @@ -305,6 +306,9 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  	if (mode->clock > max_clock)
>  		return MODE_CLOCK_HIGH;
>  
> +	if (mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;
> +
>  	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
>  	if (HAS_PCH_LPT(dev) &&
>  	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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[PATCH v3 08/11] drm/i915: TV pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to TV.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_tv.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 8b9d325..beeed25 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -897,6 +897,10 @@ intel_tv_mode_valid(struct drm_connector *connector,
 {
 	struct intel_tv *intel_tv = intel_attached_tv(connector);
 	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
+	int max_pixclk = to_i915(connector->dev)->max_dotclk;
+
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
 
 	/* Ensure TV refresh is close to desired refresh */
 	if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
-- 
1.9.1

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Re: [PATCH v3 08/11] drm/i915: TV pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:57PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to TV.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_tv.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
> index 8b9d325..beeed25 100644
> --- a/drivers/gpu/drm/i915/intel_tv.c
> +++ b/drivers/gpu/drm/i915/intel_tv.c
> @@ -897,6 +897,10 @@ intel_tv_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_tv *intel_tv = intel_attached_tv(connector);
>  	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
> +
> +	if (mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;

The mode handling in intel_tv.c seems to be a mess. But I suppose this
should be OK.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  	/* Ensure TV refresh is close to desired refresh */
>  	if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH v3 08/11] drm/i915: TV pixel clock check

[Daniel Vetter]

On Wed, Aug 12, 2015 at 09:24:01PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 31, 2015 at 03:13:57PM +0300, Mika Kahola wrote:
> > It is possible the we request to have a mode that has
> > higher pixel clock than our HW can support. This patch
> > checks if requested pixel clock is lower than the one
> > supported by the HW. The requested mode is discarded
> > if we cannot support the requested pixel clock.
> > 
> > This patch applies to TV.
> > 
> > V2:
> > - removed computation for max pixel clock
> > 
> > V3:
> > - cleanup by removing unnecessary lines
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_tv.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
> > index 8b9d325..beeed25 100644
> > --- a/drivers/gpu/drm/i915/intel_tv.c
> > +++ b/drivers/gpu/drm/i915/intel_tv.c
> > @@ -897,6 +897,10 @@ intel_tv_mode_valid(struct drm_connector *connector,
> >  {
> >  	struct intel_tv *intel_tv = intel_attached_tv(connector);
> >  	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
> > +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
> > +
> > +	if (mode->clock > max_pixclk)
> > +		return MODE_CLOCK_HIGH;
> 
> The mode handling in intel_tv.c seems to be a mess. But I suppose this
> should be OK.

We set a fake mode (which is the one userspace asks for) and the hw
internally munges it to the actual tv mode with a scaler. Except that the
frame-start/dotclock are fed from the actual TV mode (which is why
kms_flip has a check for TV modes since the timings are all wrong).

Yup, giant hairball indeed ;-)
-Daniel

> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> >  
> >  	/* Ensure TV refresh is close to desired refresh */
> >  	if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
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-- 
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[PATCH v3 09/11] drm/i915: DisplayPort-MST pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DisplayPort MST.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 585f0a4..fcf03d0 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -347,6 +347,8 @@ static enum drm_mode_status
 intel_dp_mst_mode_valid(struct drm_connector *connector,
 			struct drm_display_mode *mode)
 {
+	int max_pixclk = to_i915(connector->dev)->max_dotclk;
+
 	/* TODO - validate mode against available PBN for link */
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
@@ -354,6 +356,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		return MODE_H_ILLEGAL;
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	return MODE_OK;
 }
 
-- 
1.9.1

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Re: [PATCH v3 09/11] drm/i915: DisplayPort-MST pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:58PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DisplayPort MST.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 585f0a4..fcf03d0 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -347,6 +347,8 @@ static enum drm_mode_status
>  intel_dp_mst_mode_valid(struct drm_connector *connector,
>  			struct drm_display_mode *mode)
>  {
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk;

The pixclk vs. dotclk in every patch is tickling my ocd nerves. I'd say
pick one and stick to it everywhere. I guess I'm probably to blame here
since I've been using dotclock in the .get_config() paths, and pixclk
in the cdclk calculations. With grep I can't say which one is winning,
so I guess you could pick whichever seems more awesome.

Apart from that this patch looks good so:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  	/* TODO - validate mode against available PBN for link */
>  	if (mode->clock < 10000)
>  		return MODE_CLOCK_LOW;
> @@ -354,6 +356,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
>  	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
>  		return MODE_H_ILLEGAL;
>  
> +	if (mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;
> +
>  	return MODE_OK;
>  }
>  
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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Re: [PATCH v3 09/11] drm/i915: DisplayPort-MST pixel clock check

[Daniel Vetter]

On Wed, Aug 12, 2015 at 09:49:12PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 31, 2015 at 03:13:58PM +0300, Mika Kahola wrote:
> > It is possible the we request to have a mode that has
> > higher pixel clock than our HW can support. This patch
> > checks if requested pixel clock is lower than the one
> > supported by the HW. The requested mode is discarded
> > if we cannot support the requested pixel clock.
> > 
> > This patch applies to DisplayPort MST.
> > 
> > V2:
> > - removed computation for max pixel clock
> > 
> > V3:
> > - cleanup by removing unnecessary lines
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index 585f0a4..fcf03d0 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -347,6 +347,8 @@ static enum drm_mode_status
> >  intel_dp_mst_mode_valid(struct drm_connector *connector,
> >  			struct drm_display_mode *mode)
> >  {
> > +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
> 
> The pixclk vs. dotclk in every patch is tickling my ocd nerves. I'd say
> pick one and stick to it everywhere. I guess I'm probably to blame here
> since I've been using dotclock in the .get_config() paths, and pixclk
> in the cdclk calculations. With grep I can't say which one is winning,
> so I guess you could pick whichever seems more awesome.

+1 from me for a follow-up series to standardize on one and then maybe
even add a small DOC: kerneldoc comment explaining what all the different
clocks are that we have. We have much improved kerneldoc support now.
-Daniel

> 
> Apart from that this patch looks good so:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > +
> >  	/* TODO - validate mode against available PBN for link */
> >  	if (mode->clock < 10000)
> >  		return MODE_CLOCK_LOW;
> > @@ -354,6 +356,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
> >  	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> >  		return MODE_H_ILLEGAL;
> >  
> > +	if (mode->clock > max_pixclk)
> > +		return MODE_CLOCK_HIGH;
> > +
> >  	return MODE_OK;
> >  }
> >  
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH v3 10/11] drm/i915: DVO pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DVO.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index fd5e522..2bfc51c 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -247,6 +247,7 @@ intel_dvo_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
+	int max_pixclk = to_i915(connector->dev)->max_dotclk;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -260,6 +261,9 @@ intel_dvo_mode_valid(struct drm_connector *connector,
 			return MODE_PANEL;
 	}
 
+	if (mode->clock > max_pixclk)
+		return MODE_CLOCK_HIGH;
+
 	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
 }
 
-- 
1.9.1

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Re: [PATCH v3 10/11] drm/i915: DVO pixel clock check

[Ville Syrjälä]

On Fri, Jul 31, 2015 at 03:13:59PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DVO.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dvo.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index fd5e522..2bfc51c 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -247,6 +247,7 @@ intel_dvo_mode_valid(struct drm_connector *connector,
>  		     struct drm_display_mode *mode)
>  {
>  	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
> +	int max_pixclk = to_i915(connector->dev)->max_dotclk;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return MODE_NO_DBLESCAN;
> @@ -260,6 +261,9 @@ intel_dvo_mode_valid(struct drm_connector *connector,
>  			return MODE_PANEL;
>  	}
>  
> +	if (mode->clock > max_pixclk)
> +		return MODE_CLOCK_HIGH;

I think we'd need to check against the fixed_mode like you did for DP,
when it's present that is.

> +
>  	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
>  }
>  
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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[PATCH v3 11/11] drm/i915: Max DOT clock frequency to debugfs

[Mika Kahola]

Information on maximum supported DOT clock frequency to
i915_frequency_info.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 23a69307..4ba02b5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1314,6 +1314,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_puts(m, "no P-state info available\n");
 	}
 
+	seq_printf(m, "Max pixel clock frequency: %dkHz\n", dev_priv->max_dotclk);
+
 out:
 	intel_runtime_pm_put(dev_priv);
 	return ret;
-- 
1.9.1

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Re: [PATCH v3 11/11] drm/i915: Max DOT clock frequency to debugfs

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6910
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                 -2              302/302              300/302
SNB                                  315/315              315/315
IVB                                  336/336              336/336
BYT                                  283/283              283/283
HSW                                  378/378              378/378
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*ILK  igt@kms_flip@flip-vs-dpms-interruptible      PASS(1)      DMESG_WARN(1)
*ILK  igt@kms_flip@wf_vblank-vs-modeset-interruptible      PASS(1)      DMESG_WARN(1)
Note: You need to pay more attention to line start with '*'
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