Re: [PATCH v3 01/11] drm/i915: Store max dotclock

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, Aug 12, 2015 at 08:30:23PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 31, 2015 at 03:13:50PM +0300, Mika Kahola wrote:
> > Store max dotclock into dev_priv structure so we are able
> > to filter out the modes that are not supported by our
> > platforms.
> > 
> > V2:
> > - limit the max dot clock frequency to max CD clock frequency
> >   for the gen9 and above
> > - limit the max dot clock frequency to 90% of the max CD clock
> >   frequency for the older gens
> > - for Cherryview the max dot clock frequency is limited to 95%
> >   of the max CD clock frequency
> > - for gen2 and gen3 the max dot clock limit is set to 90% of the
> >   2X max CD clock frequency
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  1 +
> >  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
> >  2 files changed, 20 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 04aa34a..1f69211b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1777,6 +1777,7 @@ struct drm_i915_private {
> >  	unsigned int fsb_freq, mem_freq, is_ddr3;
> >  	unsigned int skl_boot_cdclk;
> >  	unsigned int cdclk_freq, max_cdclk_freq;
> > +	unsigned int max_dotclk;
> 
> nit: maybe max_dotclk_freq for extra consistentcy?
> 
> >  	unsigned int hpll_freq;
> >  
> >  	/**
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 43b0f17..c9c6d19 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5259,6 +5259,23 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
> >  			modeset_put_power_domains(dev_priv, put_domains[i]);
> >  }
> >  
> > +static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > +{
> > +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > +	int max_dotclk_freq;
> > +
> > +	if (INTEL_INFO(dev_priv)->gen >= 9)
> > +		max_dotclk_freq = max_cdclk_freq;
> > +	else if (IS_CHERRYVIEW(dev_priv))
> > +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 95, 100);
> > +	else if (INTEL_INFO(dev_priv)->gen == 2 || INTEL_INFO(dev_priv)->gen == 3)
> 
> intel_crtc_compute_config() uses 'gen < 4' as the condition around the
> double_wide handling. Maybe do the same here for consistency.
> 
> > +		max_dotclk_freq = DIV_ROUND_UP(2 * max_cdclk_freq * 90, 100);
> > +	else
> > +		max_dotclk_freq = DIV_ROUND_UP(max_cdclk_freq * 90, 100);
> 
> These should round down to match what we do in the calc_cdclk funcs.
> 
> Also to add another bikeshed color, there's no need for the local
> max_dotclk_freq variable, you can just 'return <whatever>' from each
> branch.
> 
> With at least the rounding fixed this can have
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > +
> > +	return max_dotclk_freq;
> > +}
> > +
> >  static void intel_update_max_cdclk(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -5298,6 +5315,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> >  		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
> >  	}
> >  
> > +	dev_priv->max_dotclk = intel_compute_max_dotclk(dev_priv);
> > +
> >  	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
> >  			 dev_priv->max_cdclk_freq);

Oh and I think it would be nice to add a DRM_DEBUG_DRIVER for the
compute max_dotclk so that we'll have it handy in bug reports without
having to recompute it in ones head.

> >  }
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Ville Syrjälä
Intel OTC
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