[PATCH v4 00/11] Check pixel clock when setting mode

[PATCH v4 00/11] Check pixel clock when setting mode

[Mika Kahola]

From EDID we can read and request higher pixel clock than
our HW can support. This set of patches add checks if
requested pixel clock is lower than the one supported by the HW.
The requested mode is discarded if we cannot support the requested
pixel clock. For example for Cherryview

'cvt 2560 1600 60' gives

# 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync

where pixel clock 348.50 MHz is higher than the supported 304 MHz.

The checks are implemented for DisplayPort, HDMI, LVDS, DVO, SDVO, DSI,
CRT, TV, and DP-MST.

V2:
- The maximum DOT clock frequency is added to debugfs i915_frequency_info.
- max dotclock cached in dev_priv structure
- moved computation of max dotclock to 'intel_display.c'

V3:
- intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
- for GEN9 and above the max dotclock frequency is equal to CD clock
  frequency
- for older generations the dot clock frequency is limited to 90% of the
  CD clock frequency
- For Cherryview the dot clock is limited to 95% of CD clock frequency
- for GEN2/3 the maximum dot clock frequency is limited to 90% of the
  2X CD clock frequency as we have on option to use double wide mode
- cleanup

V4:
- renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
  caused changes to all patches in my series even though some of them has
  been r-b'd by Ville
- for consistency the max_pixclk variable is renamed as max_dotclk throughout
  the whole series

Mika Kahola (11):
  drm/i915: Store max dotclock
  drm/i915: DisplayPort pixel clock check
  drm/i915: HDMI pixel clock check
  drm/i915: LVDS pixel clock check
  drm/i915: SDVO pixel clock check
  drm/i915: DSI pixel clock check
  drm/i915: CRT pixel clock check
  drm/i915: TV pixel clock check
  drm/i915: DisplayPort-MST pixel clock check
  drm/i915: DVO pixel clock check
  drm/i915: Max DOT clock frequency to debugfs

 drivers/gpu/drm/i915/i915_debugfs.c  |  2 ++
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_crt.c     |  4 ++++
 drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c      |  3 ++-
 drivers/gpu/drm/i915/intel_dp_mst.c  |  5 +++++
 drivers/gpu/drm/i915/intel_dsi.c     |  3 +++
 drivers/gpu/drm/i915/intel_dvo.c     |  3 +++
 drivers/gpu/drm/i915/intel_hdmi.c    |  8 ++++++++
 drivers/gpu/drm/i915/intel_lvds.c    | 15 +++++++++++----
 drivers/gpu/drm/i915/intel_sdvo.c    |  4 ++++
 drivers/gpu/drm/i915/intel_tv.c      |  4 ++++
 12 files changed, 66 insertions(+), 5 deletions(-)

-- 
1.9.1

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[PATCH v4 01/11] drm/i915: Store max dotclock

[Mika Kahola]

Store max dotclock into dev_priv structure so we are able
to filter out the modes that are not supported by our
platforms.

V2:
- limit the max dot clock frequency to max CD clock frequency
  for the gen9 and above
- limit the max dot clock frequency to 90% of the max CD clock
  frequency for the older gens
- for Cherryview the max dot clock frequency is limited to 95%
  of the max CD clock frequency
- for gen2 and gen3 the max dot clock limit is set to 90% of the
  2X max CD clock frequency

V3:
- max_dotclk variable renamed as max_dotclk_freq in i915_drv.h
- in intel_compute_max_dotclk() the rounding method changed from
  round up to round down when computing max dotclock

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 55611d8..e1910ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1787,6 +1787,7 @@ struct drm_i915_private {
 	unsigned int fsb_freq, mem_freq, is_ddr3;
 	unsigned int skl_boot_cdclk;
 	unsigned int cdclk_freq, max_cdclk_freq;
+	unsigned int max_dotclk_freq;
 	unsigned int hpll_freq;
 
 	/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 21aa745..e8d8860 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5275,6 +5275,20 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
 			modeset_put_power_domains(dev_priv, put_domains[i]);
 }
 
+static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
+{
+	int max_cdclk_freq = dev_priv->max_cdclk_freq;
+
+	if (INTEL_INFO(dev_priv)->gen >= 9)
+		return max_cdclk_freq;
+	else if (IS_CHERRYVIEW(dev_priv))
+		return max_cdclk_freq*95/100;
+	else if (INTEL_INFO(dev_priv)->gen < 4)
+		return 2*max_cdclk_freq*90/100;
+	else
+		return max_cdclk_freq*90/100;
+}
+
 static void intel_update_max_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5314,8 +5328,13 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
 	}
 
+	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
+
 	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
 			 dev_priv->max_cdclk_freq);
+
+	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
+			 dev_priv->max_dotclk_freq);
 }
 
 static void intel_update_cdclk(struct drm_device *dev)
-- 
1.9.1

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[PATCH v4 02/11] drm/i915: DisplayPort pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DisplayPort.

V2:
- removed computation for max DOT clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a1dac9c..f4fad4c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -206,6 +206,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	if (is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
@@ -223,7 +224,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);
 
-	if (mode_rate > max_rate)
+	if (mode_rate > max_rate || target_clock > max_dotclk)
 		return MODE_CLOCK_HIGH;
 
 	if (mode->clock < 10000)
-- 
1.9.1

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[PATCH v4 03/11] drm/i915: HDMI pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to HDMI.

V2:
- removed computation for max dot clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk
- check for stereo mode added

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 0cfbe85..e4b35dc 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1193,11 +1193,19 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 	enum drm_mode_status status;
 	int clock;
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
 
 	clock = mode->clock;
+
+	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
+		clock *= 2;
+
+	if (clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		clock *= 2;
 
-- 
1.9.1

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[PATCH v4 04/11] drm/i915: LVDS pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to LVDS.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- moved supported dotclock check from mode_valid() to intel_lvds_init()

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_lvds.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 881b5d1..06b9d1b 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -1098,8 +1098,11 @@ void intel_lvds_init(struct drm_device *dev)
 			drm_mode_debug_printmodeline(scan);
 
 			fixed_mode = drm_mode_duplicate(dev, scan);
-			if (fixed_mode)
-				goto out;
+			if (fixed_mode) {
+				if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
+					goto out;
+			}
+			fixed_mode = NULL;
 		}
 	}
 
@@ -1111,8 +1114,10 @@ void intel_lvds_init(struct drm_device *dev)
 		fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
 		if (fixed_mode) {
 			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
-			goto out;
+			if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
+				goto out;
 		}
+		fixed_mode = NULL;
 	}
 
 	/*
@@ -1135,8 +1140,10 @@ void intel_lvds_init(struct drm_device *dev)
 			DRM_DEBUG_KMS("using current (BIOS) mode: ");
 			drm_mode_debug_printmodeline(fixed_mode);
 			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
-			goto out;
+			if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
+				goto out;
 		}
+		fixed_mode = NULL;
 	}
 
 	/* If we still don't have a mode after all that, give up. */
-- 
1.9.1

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[PATCH v4 05/11] drm/i915: SDVO pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to SDVO.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index c98098e..ba00be8 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1513,6 +1513,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 		      struct drm_display_mode *mode)
 {
 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -1523,6 +1524,9 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
 	if (intel_sdvo->pixel_clock_max < mode->clock)
 		return MODE_CLOCK_HIGH;
 
+	if (mode->clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	if (intel_sdvo->is_lvds) {
 		if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
 			return MODE_PANEL;
-- 
1.9.1

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[PATCH v4 06/11] drm/i915: DSI pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DSI.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk
- moved dot clock checking inside 'if (fixed_mode)'

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4a601cf..00c6b1f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -654,6 +654,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	DRM_DEBUG_KMS("\n");
 
@@ -667,6 +668,8 @@ intel_dsi_mode_valid(struct drm_connector *connector,
 			return MODE_PANEL;
 		if (mode->vdisplay > fixed_mode->vdisplay)
 			return MODE_PANEL;
+		if (mode->clock > max_dotclk)
+			return MODE_CLOCK_HIGH;
 	}
 
 	return MODE_OK;
-- 
1.9.1

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[PATCH v4 07/11] drm/i915: CRT pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to CRT.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index af5e43b..016ca46 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -241,6 +241,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct drm_device *dev = connector->dev;
+	int max_dotclk = to_i915(dev)->max_dotclk_freq;
 
 	int max_clock = 0;
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -256,6 +257,9 @@ intel_crt_mode_valid(struct drm_connector *connector,
 	if (mode->clock > max_clock)
 		return MODE_CLOCK_HIGH;
 
+	if (mode->clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 	if (HAS_PCH_LPT(dev) &&
 	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
-- 
1.9.1

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[PATCH v4 08/11] drm/i915: TV pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to TV.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_tv.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 0568ae6..62ae1f1 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -897,6 +897,10 @@ intel_tv_mode_valid(struct drm_connector *connector,
 {
 	struct intel_tv *intel_tv = intel_attached_tv(connector);
 	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+
+	if (mode->clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
 
 	/* Ensure TV refresh is close to desired refresh */
 	if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
-- 
1.9.1

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[PATCH v4 09/11] drm/i915: DisplayPort-MST pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DisplayPort MST.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- max_pixclk variable renamed as max_dotclk

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 369f8b6..d84a837 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -347,6 +347,8 @@ static enum drm_mode_status
 intel_dp_mst_mode_valid(struct drm_connector *connector,
 			struct drm_display_mode *mode)
 {
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+
 	/* TODO - validate mode against available PBN for link */
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
@@ -354,6 +356,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		return MODE_H_ILLEGAL;
 
+	if (mode->clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	return MODE_OK;
 }
 
-- 
1.9.1

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[PATCH v4 10/11] drm/i915: DVO pixel clock check

[Mika Kahola]

It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported by the HW. The requested mode is discarded
if we cannot support the requested pixel clock.

This patch applies to DVO.

V2:
- removed computation for max pixel clock

V3:
- cleanup by removing unnecessary lines

V4:
- clock check against max dotclock moved inside 'if (fixed_mode)'

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dvo.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index dc532bb..924b724 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -201,6 +201,7 @@ intel_dvo_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
+	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -212,6 +213,8 @@ intel_dvo_mode_valid(struct drm_connector *connector,
 			return MODE_PANEL;
 		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
 			return MODE_PANEL;
+		if (mode->clock > max_dotclk)
+			return MODE_CLOCK_HIGH;
 	}
 
 	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
-- 
1.9.1

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[PATCH v4 11/11] drm/i915: Max DOT clock frequency to debugfs

[Mika Kahola]

Information on maximum supported DOT clock frequency to
i915_frequency_info.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 86734be..3df7492 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1314,6 +1314,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_puts(m, "no P-state info available\n");
 	}
 
+	seq_printf(m, "Max pixel clock frequency: %dkHz\n", dev_priv->max_dotclk_freq);
+
 out:
 	intel_runtime_pm_put(dev_priv);
 	return ret;
-- 
1.9.1

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Re: [PATCH v4 01/11] drm/i915: Store max dotclock

[Ville Syrjälä]

On Fri, Aug 14, 2015 at 01:03:21PM +0300, Mika Kahola wrote:
> Store max dotclock into dev_priv structure so we are able
> to filter out the modes that are not supported by our
> platforms.
> 
> V2:
> - limit the max dot clock frequency to max CD clock frequency
>   for the gen9 and above
> - limit the max dot clock frequency to 90% of the max CD clock
>   frequency for the older gens
> - for Cherryview the max dot clock frequency is limited to 95%
>   of the max CD clock frequency
> - for gen2 and gen3 the max dot clock limit is set to 90% of the
>   2X max CD clock frequency
> 
> V3:
> - max_dotclk variable renamed as max_dotclk_freq in i915_drv.h
> - in intel_compute_max_dotclk() the rounding method changed from
>   round up to round down when computing max dotclock
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 55611d8..e1910ec 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1787,6 +1787,7 @@ struct drm_i915_private {
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
>  	unsigned int skl_boot_cdclk;
>  	unsigned int cdclk_freq, max_cdclk_freq;
> +	unsigned int max_dotclk_freq;
>  	unsigned int hpll_freq;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 21aa745..e8d8860 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5275,6 +5275,20 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
>  			modeset_put_power_domains(dev_priv, put_domains[i]);
>  }
>  
> +static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> +{
> +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> +
> +	if (INTEL_INFO(dev_priv)->gen >= 9)

Sorry, I missed this the last time. The conditiona should
actually be (HSW || BDW || gen >= 9) or something to that effect.

Otherwise looks good, so with that fixed:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +		return max_cdclk_freq;
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		return max_cdclk_freq*95/100;
> +	else if (INTEL_INFO(dev_priv)->gen < 4)
> +		return 2*max_cdclk_freq*90/100;
> +	else
> +		return max_cdclk_freq*90/100;
> +}
> +
>  static void intel_update_max_cdclk(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5314,8 +5328,13 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>  		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
>  	}
>  
> +	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
> +
>  	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
>  			 dev_priv->max_cdclk_freq);
> +
> +	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
> +			 dev_priv->max_dotclk_freq);
>  }
>  
>  static void intel_update_cdclk(struct drm_device *dev)
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [PATCH v4 06/11] drm/i915: DSI pixel clock check

[Ville Syrjälä]

On Fri, Aug 14, 2015 at 01:03:26PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DSI.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> V4:
> - max_pixclk variable renamed as max_dotclk
> - moved dot clock checking inside 'if (fixed_mode)'
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 4a601cf..00c6b1f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -654,6 +654,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> +	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
>  
>  	DRM_DEBUG_KMS("\n");
>  
> @@ -667,6 +668,8 @@ intel_dsi_mode_valid(struct drm_connector *connector,
>  			return MODE_PANEL;
>  		if (mode->vdisplay > fixed_mode->vdisplay)
>  			return MODE_PANEL;
> +		if (mode->clock > max_dotclk)
> +			return MODE_CLOCK_HIGH;

Should be fixed_mode->clock

With that fixed:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  	}
>  
>  	return MODE_OK;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [PATCH v4 01/11] drm/i915: Store max dotclock

[Mika Kahola]

On Fri, 2015-08-14 at 15:55 +0300, Ville Syrjälä wrote:
> On Fri, Aug 14, 2015 at 01:03:21PM +0300, Mika Kahola wrote:
> > Store max dotclock into dev_priv structure so we are able
> > to filter out the modes that are not supported by our
> > platforms.
> > 
> > V2:
> > - limit the max dot clock frequency to max CD clock frequency
> >   for the gen9 and above
> > - limit the max dot clock frequency to 90% of the max CD clock
> >   frequency for the older gens
> > - for Cherryview the max dot clock frequency is limited to 95%
> >   of the max CD clock frequency
> > - for gen2 and gen3 the max dot clock limit is set to 90% of the
> >   2X max CD clock frequency
> > 
> > V3:
> > - max_dotclk variable renamed as max_dotclk_freq in i915_drv.h
> > - in intel_compute_max_dotclk() the rounding method changed from
> >   round up to round down when computing max dotclock
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  1 +
> >  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
> >  2 files changed, 20 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 55611d8..e1910ec 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1787,6 +1787,7 @@ struct drm_i915_private {
> >  	unsigned int fsb_freq, mem_freq, is_ddr3;
> >  	unsigned int skl_boot_cdclk;
> >  	unsigned int cdclk_freq, max_cdclk_freq;
> > +	unsigned int max_dotclk_freq;
> >  	unsigned int hpll_freq;
> >  
> >  	/**
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 21aa745..e8d8860 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5275,6 +5275,20 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
> >  			modeset_put_power_domains(dev_priv, put_domains[i]);
> >  }
> >  
> > +static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > +{
> > +	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > +
> > +	if (INTEL_INFO(dev_priv)->gen >= 9)
> 
> Sorry, I missed this the last time. The conditiona should
> actually be (HSW || BDW || gen >= 9) or something to that effect.

Allright. I add Haswell and Broadwell to this condition.

-Mika-

> Otherwise looks good, so with that fixed:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> > +		return max_cdclk_freq;
> > +	else if (IS_CHERRYVIEW(dev_priv))
> > +		return max_cdclk_freq*95/100;
> > +	else if (INTEL_INFO(dev_priv)->gen < 4)
> > +		return 2*max_cdclk_freq*90/100;
> > +	else
> > +		return max_cdclk_freq*90/100;
> > +}
> > +
> >  static void intel_update_max_cdclk(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -5314,8 +5328,13 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> >  		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
> >  	}
> >  
> > +	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
> > +
> >  	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
> >  			 dev_priv->max_cdclk_freq);
> > +
> > +	DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
> > +			 dev_priv->max_dotclk_freq);
> >  }
> >  
> >  static void intel_update_cdclk(struct drm_device *dev)
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [PATCH v4 04/11] drm/i915: LVDS pixel clock check

[Ville Syrjälä]

On Fri, Aug 14, 2015 at 01:03:24PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to LVDS.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> V4:
> - moved supported dotclock check from mode_valid() to intel_lvds_init()
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lvds.c | 15 +++++++++++----
>  1 file changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 881b5d1..06b9d1b 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -1098,8 +1098,11 @@ void intel_lvds_init(struct drm_device *dev)
>  			drm_mode_debug_printmodeline(scan);
>  
>  			fixed_mode = drm_mode_duplicate(dev, scan);
> -			if (fixed_mode)
> -				goto out;
> +			if (fixed_mode) {
> +				if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
> +					goto out;
> +			}
> +			fixed_mode = NULL;
>  		}
>  	}
>  
> @@ -1111,8 +1114,10 @@ void intel_lvds_init(struct drm_device *dev)
>  		fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
>  		if (fixed_mode) {
>  			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
> -			goto out;
> +			if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
> +				goto out;
>  		}
> +		fixed_mode = NULL;
>  	}
>  
>  	/*
> @@ -1135,8 +1140,10 @@ void intel_lvds_init(struct drm_device *dev)
>  			DRM_DEBUG_KMS("using current (BIOS) mode: ");
>  			drm_mode_debug_printmodeline(fixed_mode);
>  			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
> -			goto out;
> +			if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
> +				goto out;
>  		}
> +		fixed_mode = NULL;

I don't think we want to special case just LVDS this way. Whatever we do
with fixed_mode validation should be done for all connector types that
have it. For now I think we can more or less ignore the issue.

So in that light, your previous patch was OK except it should have just
checked fixed_mode->clock instead of mode->clock. Sorry if my ramblings
confused you too much.

>  	}
>  
>  	/* If we still don't have a mode after all that, give up. */
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH v4 10/11] drm/i915: DVO pixel clock check

[Ville Syrjälä]

On Fri, Aug 14, 2015 at 01:03:30PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to DVO.
> 
> V2:
> - removed computation for max pixel clock
> 
> V3:
> - cleanup by removing unnecessary lines
> 
> V4:
> - clock check against max dotclock moved inside 'if (fixed_mode)'
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dvo.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index dc532bb..924b724 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -201,6 +201,7 @@ intel_dvo_mode_valid(struct drm_connector *connector,
>  		     struct drm_display_mode *mode)
>  {
>  	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
> +	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return MODE_NO_DBLESCAN;
> @@ -212,6 +213,8 @@ intel_dvo_mode_valid(struct drm_connector *connector,
>  			return MODE_PANEL;
>  		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
>  			return MODE_PANEL;
> +		if (mode->clock > max_dotclk)
> +			return MODE_CLOCK_HIGH;
>  	}

What we want here is duplicate the intel_dp.c logic exactly, ie. check
against fixed_mode->clock when it's around, otherwise check against
mode->clock.

>  
>  	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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-- 
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Re: [PATCH v4 00/11] Check pixel clock when setting mode

[Daniel Vetter]

On Fri, Aug 14, 2015 at 01:03:20PM +0300, Mika Kahola wrote:
> From EDID we can read and request higher pixel clock than
> our HW can support. This set of patches add checks if
> requested pixel clock is lower than the one supported by the HW.
> The requested mode is discarded if we cannot support the requested
> pixel clock. For example for Cherryview
> 
> 'cvt 2560 1600 60' gives
> 
> # 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
> Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync
> 
> where pixel clock 348.50 MHz is higher than the supported 304 MHz.
> 
> The checks are implemented for DisplayPort, HDMI, LVDS, DVO, SDVO, DSI,
> CRT, TV, and DP-MST.
> 
> V2:
> - The maximum DOT clock frequency is added to debugfs i915_frequency_info.
> - max dotclock cached in dev_priv structure
> - moved computation of max dotclock to 'intel_display.c'
> 
> V3:
> - intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
> - for GEN9 and above the max dotclock frequency is equal to CD clock
>   frequency
> - for older generations the dot clock frequency is limited to 90% of the
>   CD clock frequency
> - For Cherryview the dot clock is limited to 95% of CD clock frequency
> - for GEN2/3 the maximum dot clock frequency is limited to 90% of the
>   2X CD clock frequency as we have on option to use double wide mode
> - cleanup
> 
> V4:
> - renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
>   caused changes to all patches in my series even though some of them has
>   been r-b'd by Ville
> - for consistency the max_pixclk variable is renamed as max_dotclk throughout
>   the whole series

One thing that was completely missed here is testcases? Do they exist?
-Daniel

> 
> Mika Kahola (11):
>   drm/i915: Store max dotclock
>   drm/i915: DisplayPort pixel clock check
>   drm/i915: HDMI pixel clock check
>   drm/i915: LVDS pixel clock check
>   drm/i915: SDVO pixel clock check
>   drm/i915: DSI pixel clock check
>   drm/i915: CRT pixel clock check
>   drm/i915: TV pixel clock check
>   drm/i915: DisplayPort-MST pixel clock check
>   drm/i915: DVO pixel clock check
>   drm/i915: Max DOT clock frequency to debugfs
> 
>  drivers/gpu/drm/i915/i915_debugfs.c  |  2 ++
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/intel_crt.c     |  4 ++++
>  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c      |  3 ++-
>  drivers/gpu/drm/i915/intel_dp_mst.c  |  5 +++++
>  drivers/gpu/drm/i915/intel_dsi.c     |  3 +++
>  drivers/gpu/drm/i915/intel_dvo.c     |  3 +++
>  drivers/gpu/drm/i915/intel_hdmi.c    |  8 ++++++++
>  drivers/gpu/drm/i915/intel_lvds.c    | 15 +++++++++++----
>  drivers/gpu/drm/i915/intel_sdvo.c    |  4 ++++
>  drivers/gpu/drm/i915/intel_tv.c      |  4 ++++
>  12 files changed, 66 insertions(+), 5 deletions(-)
> 
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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http://blog.ffwll.ch
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Re: [PATCH v4 04/11] drm/i915: LVDS pixel clock check

[Mika Kahola]

On Fri, 2015-08-14 at 16:09 +0300, Ville Syrjälä wrote:
> On Fri, Aug 14, 2015 at 01:03:24PM +0300, Mika Kahola wrote:
> > It is possible the we request to have a mode that has
> > higher pixel clock than our HW can support. This patch
> > checks if requested pixel clock is lower than the one
> > supported by the HW. The requested mode is discarded
> > if we cannot support the requested pixel clock.
> > 
> > This patch applies to LVDS.
> > 
> > V2:
> > - removed computation for max pixel clock
> > 
> > V3:
> > - cleanup by removing unnecessary lines
> > 
> > V4:
> > - moved supported dotclock check from mode_valid() to intel_lvds_init()
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_lvds.c | 15 +++++++++++----
> >  1 file changed, 11 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> > index 881b5d1..06b9d1b 100644
> > --- a/drivers/gpu/drm/i915/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/intel_lvds.c
> > @@ -1098,8 +1098,11 @@ void intel_lvds_init(struct drm_device *dev)
> >  			drm_mode_debug_printmodeline(scan);
> >  
> >  			fixed_mode = drm_mode_duplicate(dev, scan);
> > -			if (fixed_mode)
> > -				goto out;
> > +			if (fixed_mode) {
> > +				if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
> > +					goto out;
> > +			}
> > +			fixed_mode = NULL;
> >  		}
> >  	}
> >  
> > @@ -1111,8 +1114,10 @@ void intel_lvds_init(struct drm_device *dev)
> >  		fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
> >  		if (fixed_mode) {
> >  			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
> > -			goto out;
> > +			if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
> > +				goto out;
> >  		}
> > +		fixed_mode = NULL;
> >  	}
> >  
> >  	/*
> > @@ -1135,8 +1140,10 @@ void intel_lvds_init(struct drm_device *dev)
> >  			DRM_DEBUG_KMS("using current (BIOS) mode: ");
> >  			drm_mode_debug_printmodeline(fixed_mode);
> >  			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
> > -			goto out;
> > +			if (fixed_mode->clock <= dev_priv->max_dotclk_freq)
> > +				goto out;
> >  		}
> > +		fixed_mode = NULL;
> 
> I don't think we want to special case just LVDS this way. Whatever we do
> with fixed_mode validation should be done for all connector types that
> have it. For now I think we can more or less ignore the issue.
> 
> So in that light, your previous patch was OK except it should have just
> checked fixed_mode->clock instead of mode->clock. Sorry if my ramblings
> confused you too much.
> 
No worries. I was a bit unsure if this check should have been done in
init anyway. I'll take a step back and modify the previous patch.

-Mika-
> >  	}
> >  
> >  	/* If we still don't have a mode after all that, give up. */
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [PATCH v4 04/11] drm/i915: LVDS pixel clock check

[Lukas Wunner]

Hi Mika,

On Fri, Aug 14, 2015 at 01:03:24PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot support the requested pixel clock.
> 
> This patch applies to LVDS.

The spec lists maximum dot clocks for each connector type.
Here's the spec for IVB for instance (see section 2.3):
https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part4.pdf

E.g. for LVDS it's 224 MHz, for DP it's 270 MHz.
If this is identical across all generations (which I haven't checked,
but seems likely), you can use these constant values, which would be
more accurate than just using the same dev_priv->max_cdclk_freq for
all connector types.

Best regards,

Lukas
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Re: [PATCH v4 11/11] drm/i915: Max DOT clock frequency to debugfs

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 7199
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  302/302              302/302
SNB                                  315/315              315/315
IVB                                  336/336              336/336
BYT                 -1              283/283              282/283
HSW                                  378/378              378/378
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*BYT  igt@gem_partial_pwrite_pread@reads-uncached      PASS(1)      FAIL(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH v4 00/11] Check pixel clock when setting mode

[Mika Kahola]

On Fri, 2015-08-14 at 15:13 +0200, Daniel Vetter wrote:
> On Fri, Aug 14, 2015 at 01:03:20PM +0300, Mika Kahola wrote:
> > From EDID we can read and request higher pixel clock than
> > our HW can support. This set of patches add checks if
> > requested pixel clock is lower than the one supported by the HW.
> > The requested mode is discarded if we cannot support the requested
> > pixel clock. For example for Cherryview
> > 
> > 'cvt 2560 1600 60' gives
> > 
> > # 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
> > Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync
> > 
> > where pixel clock 348.50 MHz is higher than the supported 304 MHz.
> > 
> > The checks are implemented for DisplayPort, HDMI, LVDS, DVO, SDVO, DSI,
> > CRT, TV, and DP-MST.
> > 
> > V2:
> > - The maximum DOT clock frequency is added to debugfs i915_frequency_info.
> > - max dotclock cached in dev_priv structure
> > - moved computation of max dotclock to 'intel_display.c'
> > 
> > V3:
> > - intel_update_max_dotclk() renamed as intel_compute_max_dotclk()
> > - for GEN9 and above the max dotclock frequency is equal to CD clock
> >   frequency
> > - for older generations the dot clock frequency is limited to 90% of the
> >   CD clock frequency
> > - For Cherryview the dot clock is limited to 95% of CD clock frequency
> > - for GEN2/3 the maximum dot clock frequency is limited to 90% of the
> >   2X CD clock frequency as we have on option to use double wide mode
> > - cleanup
> > 
> > V4:
> > - renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h)
> >   caused changes to all patches in my series even though some of them has
> >   been r-b'd by Ville
> > - for consistency the max_pixclk variable is renamed as max_dotclk throughout
> >   the whole series
> 
> One thing that was completely missed here is testcases? Do they exist?
> -Daniel
Yes, the testcases are still missing.

-Mika-


> > 
> > Mika Kahola (11):
> >   drm/i915: Store max dotclock
> >   drm/i915: DisplayPort pixel clock check
> >   drm/i915: HDMI pixel clock check
> >   drm/i915: LVDS pixel clock check
> >   drm/i915: SDVO pixel clock check
> >   drm/i915: DSI pixel clock check
> >   drm/i915: CRT pixel clock check
> >   drm/i915: TV pixel clock check
> >   drm/i915: DisplayPort-MST pixel clock check
> >   drm/i915: DVO pixel clock check
> >   drm/i915: Max DOT clock frequency to debugfs
> > 
> >  drivers/gpu/drm/i915/i915_debugfs.c  |  2 ++
> >  drivers/gpu/drm/i915/i915_drv.h      |  1 +
> >  drivers/gpu/drm/i915/intel_crt.c     |  4 ++++
> >  drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_dp.c      |  3 ++-
> >  drivers/gpu/drm/i915/intel_dp_mst.c  |  5 +++++
> >  drivers/gpu/drm/i915/intel_dsi.c     |  3 +++
> >  drivers/gpu/drm/i915/intel_dvo.c     |  3 +++
> >  drivers/gpu/drm/i915/intel_hdmi.c    |  8 ++++++++
> >  drivers/gpu/drm/i915/intel_lvds.c    | 15 +++++++++++----
> >  drivers/gpu/drm/i915/intel_sdvo.c    |  4 ++++
> >  drivers/gpu/drm/i915/intel_tv.c      |  4 ++++
> >  12 files changed, 66 insertions(+), 5 deletions(-)
> > 
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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