From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes
Date: Wed, 26 Aug 2015 11:16:34 +0200 [thread overview]
Message-ID: <20150826091634.GQ20434@phenom.ffwll.local> (raw)
In-Reply-To: <1440169721-25861-1-git-send-email-chris@chris-wilson.co.uk>
On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> In order to flush the results from in-batch pipecontrol writes (used for
> example in glQuery) before declaring the batch complete (and so declaring
> the query results coherent), we need to set the FlushEnable bit in our
> flushing pipecontrol. The FlushEnable bit "waits until all previous
> writes of immediate data from post-sync circles are complete before
> executing the next command".
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: stable@vger.kernel.org
Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
bugzilla or why is this cc: stable?
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 01cf0ca21990..e0c19d75b196 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1771,6 +1771,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> if (invalidate_domains) {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c2392f6c4204..551af7399ca1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -330,6 +330,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> @@ -401,6 +402,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
next prev parent reply other threads:[~2015-08-26 9:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-21 15:08 [PATCH] drm/i915: Flush pipecontrol post-sync writes Chris Wilson
2015-08-21 15:21 ` Ville Syrjälä
2015-08-26 9:16 ` Daniel Vetter [this message]
2015-08-26 9:29 ` [Intel-gfx] " Chris Wilson
2015-10-13 12:45 ` Jani Nikula
2015-10-13 13:37 ` Daniel Vetter
2015-10-13 13:57 ` [Intel-gfx] " Jani Nikula
2015-08-29 2:22 ` shuang.he
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