Re: [PATCH v2 3/3] drm/i915/dp: move TPS3 logic to where it's used

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Aug 27, 2015 at 01:25:38PM +0300, Jani Nikula wrote:
> There is no need to have a separate flag for tps3 as the information is
> only used at one location. Move the logic there to make it easier to
> follow.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 31 +++++++++++++++++--------------
>  drivers/gpu/drm/i915/intel_drv.h |  1 -
>  2 files changed, 17 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 50ba527763e9..12bce36065a1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3848,13 +3848,25 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  void
>  intel_dp_complete_link_train(struct intel_dp *intel_dp)
>  {
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = dig_port->base.base.dev;
>  	bool channel_eq = false;
>  	int tries, cr_tries;
>  	uint32_t DP = intel_dp->DP;
>  	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>  
> -	/* Training Pattern 3 for HBR2 or 1.2 devices that support it*/
> -	if (intel_dp->link_rate == 540000 || intel_dp->use_tps3)
> +	/*
> +	 * Training Pattern 3 for HBR2 or 1.2 devices that support it.
> +	 *
> +	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
> +	 * also mandatory for downstream devices that support HBR2.
> +	 *
> +	 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
> +	 * supported but still not enabled.
> +	 */
> +	if (intel_dp->link_rate == 540000 ||
> +	    (intel_dp_source_supports_hbr2(dev) &&
> +	     intel_dp_tps3_supported(intel_dp->dpcd)))

I'm thinking we could just kill the link_rate check here. It would
only make a difference if the sink lied in its DPCD.

>  		training_pattern = DP_TRAINING_PATTERN_3;
>  
>  	/* channel equalization */
> @@ -4036,18 +4048,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  		}
>  	}
>  
> -	/* Training Pattern 3 support, Intel platforms that support HBR2 alone
> -	 * have support for TP3 hence that check is used along with dpcd check
> -	 * to ensure TP3 can be enabled.
> -	 * SKL < B0: due it's WaDisableHBR2 is the only exception where TP3 is
> -	 * supported but still not enabled.
> -	 */
> -	if (intel_dp_tps3_supported(intel_dp->dpcd) &&
> -	    intel_dp_source_supports_hbr2(dev)) {
> -		intel_dp->use_tps3 = true;
> -		DRM_DEBUG_KMS("Displayport TPS3 supported\n");
> -	} else
> -		intel_dp->use_tps3 = false;
> +	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
> +		      intel_dp_source_supports_hbr2(dev) ? "yes" : "no",
> +		      intel_dp_tps3_supported(intel_dp->dpcd) ? "yes" : "no");

I guess we don't have a one true yesno() macro. I think we have such
things in specific files. Maybe make it available everywhere?

But anyway, those are just food for thought, and the series looks good
so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  	/* Intermediate frequency support */
>  	if (is_edp(intel_dp) &&
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c61ba47eda7c..fa9840fbccba 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -744,7 +744,6 @@ struct intel_dp {
>  	enum pipe pps_pipe;
>  	struct edp_power_seq pps_delays;
>  
> -	bool use_tps3;
>  	bool can_mst; /* this port supports mst */
>  	bool is_mst;
>  	int active_mst_links;
> -- 
> 2.1.4
> 
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-- 
Ville Syrjälä
Intel OTC
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