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From: Daniel Vetter <daniel@ffwll.ch>
To: Francisco Jerez <currojerez@riseup.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915: Fix command parser to validate multiple register access with the same command.
Date: Tue, 1 Sep 2015 11:41:24 +0200	[thread overview]
Message-ID: <20150901094124.GL1367@phenom.ffwll.local> (raw)
In-Reply-To: <87fv304dx8.fsf@riseup.net>

On Mon, Aug 31, 2015 at 01:19:47AM +0300, Francisco Jerez wrote:
> Francisco Jerez <currojerez@riseup.net> writes:
> 
> > Daniel Vetter <daniel@ffwll.ch> writes:
> >
> >> On Mon, Jun 15, 2015 at 02:26:22PM +0300, Ville Syrjälä wrote:
> >>> On Mon, Jun 15, 2015 at 02:18:01PM +0300, Francisco Jerez wrote:
> >>> > Daniel Vetter <daniel@ffwll.ch> writes:
> >>> > 
> >>> > > On Tue, Jun 02, 2015 at 05:36:26PM +0800, Zhigang Gong wrote:
> >>> > >> The patchset LGTM and works well with beignet. The 80%+ performance regression issue in darktable also has been fixed
> >>> > >> after this patchset applied and enable the atomic in L3 at beignet side. So,
> >>> > >> 
> >>> > >> Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
> >>> > >
> >>> > > All three merged.
> >>> > 
> >>> > Thanks Daniel.
> >>> > 
> >>> > > Aside: Dont we need an increment for the cmd parser version for
> >>> > > userspace to be able to detect this?
> >>> > >
> >>> > Yeah, that would be a good idea, patch attached.
> >>> 
> >>> The old version alloweed userspace to write basically any register, the
> >>> new version allows only the whitelisted registers. I don't see how a
> >>> version number bump would help anyone.
> >>
> >> Oops, totally missed the context of patch 1. Jani I think that one's for
> >> you too ...
> >>
> > IMHO the version bump is still useful for userspace to find out whether
> > it can use plain LRIs to write the L3 atomic chicken bits.  It's true
> > that as Ville said it would have been possible for userspace to write
> > the same bits before this series by building a batch specifically
> > crafted to cheat the command parser, but I don't think we want userspace
> > to rely on a command parser bug (e.g. because we may want to back-port
> > the fix to earlier kernel versions).
> >
> Ping.  I cannot use these registers from userspace until the command
> parser version number is bumped.

Queued for -next, thanks for the patch.
-Daniel

> 
> >> Thanks for pointing this out.
> >> -Daniel
> >> -- 
> >> Daniel Vetter
> >> Software Engineer, Intel Corporation
> >> http://blog.ffwll.ch
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx




-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2015-09-01  9:41 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-29 13:44 [PATCH 1/3] drm/i915: Fix command parser to validate multiple register access with the same command Francisco Jerez
2015-05-29 13:44 ` [PATCH 2/3] drm/i915: Extend the parser to check register writes against a mask/value pair Francisco Jerez
2015-05-29 13:44 ` [PATCH 3/3] drm/i915: Add SCRATCH1 and ROW_CHICKEN3 to the register whitelist Francisco Jerez
2015-06-02  9:36 ` [PATCH 1/3] drm/i915: Fix command parser to validate multiple register access with the same command Zhigang Gong
2015-06-02 11:02   ` Francisco Jerez
2015-06-15 10:35   ` Daniel Vetter
2015-06-15 11:18     ` Francisco Jerez
2015-06-15 11:26       ` Ville Syrjälä
2015-06-15 11:40         ` Daniel Vetter
2015-06-15 12:05           ` Francisco Jerez
2015-08-30 22:19             ` Francisco Jerez
2015-09-01  9:41               ` Daniel Vetter [this message]
2015-06-15 13:15           ` Jani Nikula

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