[PATCH] drm/i915: access the PP_ON_DELAYS/PP_OFF_DELAYS regs only pre GEN5

[PATCH] drm/i915: access the PP_ON_DELAYS/PP_OFF_DELAYS regs only pre GEN5

[Imre Deak]

These registers exist only before GEN5, so currently we may access
undefined registers on VLV/CHV and BXT. Apply the workaround only pre
GEN5.

This triggered an unclaimed register access warning on BXT.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b3e437b..8969fe6 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1349,7 +1349,7 @@ void intel_setup_bios(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	 /* Set the Panel Power On/Off timings if uninitialized. */
-	if (!HAS_PCH_SPLIT(dev) &&
+	if (INTEL_INFO(dev_priv)->gen < 5 &&
 	    I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
 		/* Set T2 to 40ms and T5 to 200ms */
 		I915_WRITE(PP_ON_DELAYS, 0x019007d0);
-- 
2.1.4

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Re: [PATCH] drm/i915: access the PP_ON_DELAYS/PP_OFF_DELAYS regs only pre GEN5

[Ville Syrjälä]

On Wed, Sep 02, 2015 at 06:36:35PM +0300, Imre Deak wrote:
> These registers exist only before GEN5, so currently we may access
> undefined registers on VLV/CHV and BXT. Apply the workaround only pre
> GEN5.
> 
> This triggered an unclaimed register access warning on BXT.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_bios.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index b3e437b..8969fe6 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1349,7 +1349,7 @@ void intel_setup_bios(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	 /* Set the Panel Power On/Off timings if uninitialized. */
> -	if (!HAS_PCH_SPLIT(dev) &&
> +	if (INTEL_INFO(dev_priv)->gen < 5 &&
>  	    I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
>  		/* Set T2 to 40ms and T5 to 200ms */
>  		I915_WRITE(PP_ON_DELAYS, 0x019007d0);

What a nasty place to hide it. Could you move this somewhere into the
LVDS init code so that it's less well hidden? And maybe toss in a debug
message indicating we had to pull the panel delays from thin air.

-- 
Ville Syrjälä
Intel OTC
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