[PATCH 0/4] DSI Dual link enabling on BXT

[PATCH 0/4] DSI Dual link enabling on BXT

[Gaurav K Singh]

Hi,

These patches enable DSI dual link mode on BXT boards. These set of patches
build on top of the floated DSI Video mode patches on BXT (Uma's patches).

Regards
Gaurav

Gaurav K Singh (4):
  drm/i915: Enable dual link mode in BXT
  drm/i915: Use adjusted mode clk for calculating DSI clk
  drm/i915: Execute RESET sequence before device ready
  drm/i915: Program vactive & hactive display size for both ports

 drivers/gpu/drm/i915/i915_reg.h            |    7 +++---
 drivers/gpu/drm/i915/intel_display.c       |   37 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.c           |   11 ++++++---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   15 +++++++++++
 drivers/gpu/drm/i915/intel_dsi_pll.c       |    4 ++-
 include/drm/drm_panel.h                    |    9 +++++++
 6 files changed, 76 insertions(+), 7 deletions(-)

-- 
1.7.9.5

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[PATCH 1/4] drm/i915: Enable dual link mode in BXT

[Gaurav K Singh]

Enable BIT 0 of MIPI Port Ctrl reg to enable dual link mode.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |    7 ++++---
 drivers/gpu/drm/i915/intel_dsi.c |    9 ++++++---
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1ea4686..4e5c0bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7581,17 +7581,17 @@ enum skl_disp_power_wells {
 /* BXT MIPI mode configure */
 #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
 #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
-#define  BXT_MIPI_TRANS_HACTIVE(tc)	_MIPI_PORT(tc, \
+#define  BXT_MIPI_TRANS_HACTIVE(port)	_MIPI_PORT(port, \
 		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
 
 #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
 #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
-#define  BXT_MIPI_TRANS_VACTIVE(tc)	_MIPI_PORT(tc, \
+#define  BXT_MIPI_TRANS_VACTIVE(port)	_MIPI_PORT(port, \
 		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
 
 #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
 #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
-#define  BXT_MIPI_TRANS_VTOTAL(tc)	_MIPI_PORT(tc, \
+#define  BXT_MIPI_TRANS_VTOTAL(port)	_MIPI_PORT(port, \
 		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
 
 #define BXT_DSI_PLL_CTL			0x161000
@@ -7665,6 +7665,7 @@ enum skl_disp_power_wells {
 #define  LANE_CONFIGURATION_4LANE			(0 << 0)
 #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
 #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
+#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE		(1 << 0)
 
 #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
 #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 2ccbda5..ec7e48b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -400,9 +400,12 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 		if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
 			temp |= (intel_dsi->dual_link - 1)
 						<< DUAL_LINK_MODE_SHIFT;
-			temp |= intel_crtc->pipe ?
-					LANE_CONFIGURATION_DUAL_LINK_B :
-					LANE_CONFIGURATION_DUAL_LINK_A;
+			if (IS_VALLEYVIEW(dev))
+				temp |= intel_crtc->pipe ?
+						LANE_CONFIGURATION_DUAL_LINK_B :
+						LANE_CONFIGURATION_DUAL_LINK_A;
+			else if (IS_BROXTON(dev))
+				temp |= LANE_CONFIGURATION_DUAL_LINK_ENABLE;
 		}
 		/* assert ip_tg_enable signal */
 		I915_WRITE(port_ctrl, temp | DPI_ENABLE);
-- 
1.7.9.5

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[PATCH 2/4] drm/i915: Use adjusted mode clk for calculating DSI clk

[Gaurav K Singh]

Earlier, pclk was getting used for calculating DSI clk. For single link
MIPI panels, it will work fine. But for dual link MIPI, since pclk gets
halved, DSI clk will have a wrong value.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index bf0f622..a53ccc9 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -468,12 +468,14 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
 static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u8 dsi_ratio;
 	u32 dsi_clk;
 	u32 val;
 
-	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
+	dsi_clk = dsi_clk_from_pclk(mode->clock, intel_dsi->pixel_format,
 			intel_dsi->lane_count);
 
 	/*
-- 
1.7.9.5

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[PATCH 3/4] drm/i915: Execute RESET sequence before device ready

[Gaurav K Singh]

Before setting the MIPI device to ready state, execute the RESET
sequence.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c           |    2 ++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   15 +++++++++++++++
 include/drm/drm_panel.h                    |    9 +++++++++
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index ec7e48b..d7e2118 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -497,6 +497,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 		I915_WRITE(DSPCLK_GATE_D, tmp);
 	}
 
+	drm_panel_reset(intel_dsi->panel);
+
 	/* put device in ready state */
 	intel_dsi_device_ready(encoder);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a5e99ac..feeca59 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -292,6 +292,20 @@ static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
 	}
 }
 
+static int vbt_panel_reset(struct drm_panel *panel)
+{
+	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
+	struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	const u8 *sequence;
+
+	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
+	generic_exec_sequence(intel_dsi, sequence);
+
+	return 0;
+}
+
 static int vbt_panel_prepare(struct drm_panel *panel)
 {
 	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
@@ -377,6 +391,7 @@ static const struct drm_panel_funcs vbt_panel_funcs = {
 	.disable = vbt_panel_disable,
 	.unprepare = vbt_panel_unprepare,
 	.prepare = vbt_panel_prepare,
+	.reset = vbt_panel_reset,
 	.enable = vbt_panel_enable,
 	.get_modes = vbt_panel_get_modes,
 };
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 13ff44b..1e2432e 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -68,6 +68,7 @@ struct display_timing;
 struct drm_panel_funcs {
 	int (*disable)(struct drm_panel *panel);
 	int (*unprepare)(struct drm_panel *panel);
+	int (*reset)(struct drm_panel *panel);
 	int (*prepare)(struct drm_panel *panel);
 	int (*enable)(struct drm_panel *panel);
 	int (*get_modes)(struct drm_panel *panel);
@@ -101,6 +102,14 @@ static inline int drm_panel_disable(struct drm_panel *panel)
 	return panel ? -ENOSYS : -EINVAL;
 }
 
+static inline int drm_panel_reset(struct drm_panel *panel)
+{
+	if (panel && panel->funcs && panel->funcs->prepare)
+		return panel->funcs->reset(panel);
+
+	return panel ? -ENOSYS : -EINVAL;
+}
+
 static inline int drm_panel_prepare(struct drm_panel *panel)
 {
 	if (panel && panel->funcs && panel->funcs->prepare)
-- 
1.7.9.5

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[PATCH 4/4] drm/i915: Program vactive & hactive display size for both ports

[Gaurav K Singh]

Program the required mmio regs for hactive and vactive display size.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   37 ++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ab9f06a..0285af9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7653,6 +7653,7 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+	bool is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
 	uint32_t tmp;
 
 	tmp = I915_READ(HTOTAL(cpu_transcoder));
@@ -7681,6 +7682,25 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
 		pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
 	}
 
+	 if (IS_BROXTON(dev) && is_dsi) {
+		struct intel_encoder *encoder;
+
+		for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
+			struct intel_dsi *intel_dsi =
+				enc_to_intel_dsi(&encoder->base);
+			enum port port;
+
+			for_each_dsi_port(port, intel_dsi->ports) {
+				pipe_config->base.adjusted_mode.crtc_hdisplay =
+						I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
+				pipe_config->base.adjusted_mode.crtc_vdisplay =
+						I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
+				pipe_config->base.adjusted_mode.crtc_vtotal =
+						I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
+			}
+		}
+	}
+
 	tmp = I915_READ(PIPESRC(crtc->pipe));
 	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
 	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
@@ -10569,6 +10589,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 	int vtot = I915_READ(VTOTAL(cpu_transcoder));
 	int vsync = I915_READ(VSYNC(cpu_transcoder));
 	enum pipe pipe = intel_crtc->pipe;
+	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
 
 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
 	if (!mode)
@@ -10598,6 +10619,22 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 	mode->vsync_start = (vsync & 0xffff) + 1;
 	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
 
+	if (IS_BROXTON(dev) && is_dsi) {
+		struct intel_encoder *encoder;
+
+		for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
+			struct intel_dsi *intel_dsi =
+						enc_to_intel_dsi(&encoder->base);
+			enum port port;
+
+			for_each_dsi_port(port, intel_dsi->ports) {
+				mode->vtotal = I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
+				mode->hdisplay = I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
+				mode->vdisplay = I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
+			}
+		}
+	}
+
 	drm_mode_set_name(mode);
 
 	return mode;
-- 
1.7.9.5

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Re: [PATCH 1/4] drm/i915: Enable dual link mode in BXT

[Ville Syrjälä]

On Wed, Sep 16, 2015 at 02:48:38PM +0530, Gaurav K Singh wrote:
> Enable BIT 0 of MIPI Port Ctrl reg to enable dual link mode.
> 
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |    7 ++++---
>  drivers/gpu/drm/i915/intel_dsi.c |    9 ++++++---
>  2 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1ea4686..4e5c0bb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7581,17 +7581,17 @@ enum skl_disp_power_wells {
>  /* BXT MIPI mode configure */
>  #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
>  #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
> -#define  BXT_MIPI_TRANS_HACTIVE(tc)	_MIPI_PORT(tc, \
> +#define  BXT_MIPI_TRANS_HACTIVE(port)	_MIPI_PORT(port, \
>  		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
>  
>  #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
>  #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
> -#define  BXT_MIPI_TRANS_VACTIVE(tc)	_MIPI_PORT(tc, \
> +#define  BXT_MIPI_TRANS_VACTIVE(port)	_MIPI_PORT(port, \
>  		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
>  
>  #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
>  #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
> -#define  BXT_MIPI_TRANS_VTOTAL(tc)	_MIPI_PORT(tc, \
> +#define  BXT_MIPI_TRANS_VTOTAL(port)	_MIPI_PORT(port, \
>  		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
>  
>  #define BXT_DSI_PLL_CTL			0x161000
> @@ -7665,6 +7665,7 @@ enum skl_disp_power_wells {
>  #define  LANE_CONFIGURATION_4LANE			(0 << 0)
>  #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
>  #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
> +#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE		(1 << 0)
>  
>  #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
>  #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 2ccbda5..ec7e48b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -400,9 +400,12 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  		if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
>  			temp |= (intel_dsi->dual_link - 1)
>  						<< DUAL_LINK_MODE_SHIFT;
> -			temp |= intel_crtc->pipe ?
> -					LANE_CONFIGURATION_DUAL_LINK_B :
> -					LANE_CONFIGURATION_DUAL_LINK_A;
> +			if (IS_VALLEYVIEW(dev))
> +				temp |= intel_crtc->pipe ?
> +						LANE_CONFIGURATION_DUAL_LINK_B :
> +						LANE_CONFIGURATION_DUAL_LINK_A;
> +			else if (IS_BROXTON(dev))
> +				temp |= LANE_CONFIGURATION_DUAL_LINK_ENABLE;
>  		}
>  		/* assert ip_tg_enable signal */
>  		I915_WRITE(port_ctrl, temp | DPI_ENABLE);
> -- 
> 1.7.9.5
> 
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 2/4] drm/i915: Use adjusted mode clk for calculating DSI clk

[Ville Syrjälä]

On Wed, Sep 16, 2015 at 02:48:39PM +0530, Gaurav K Singh wrote:
> Earlier, pclk was getting used for calculating DSI clk. For single link
> MIPI panels, it will work fine. But for dual link MIPI, since pclk gets
> halved, DSI clk will have a wrong value.

Shouldn't we then do pclk*!!dual_link. pclk can be higher than the
dotclock due to the pixel overlap / burst mode stuff, no?

> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index bf0f622..a53ccc9 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -468,12 +468,14 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
>  static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u8 dsi_ratio;
>  	u32 dsi_clk;
>  	u32 val;
>  
> -	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> +	dsi_clk = dsi_clk_from_pclk(mode->clock, intel_dsi->pixel_format,
>  			intel_dsi->lane_count);
>  
>  	/*
> -- 
> 1.7.9.5
> 
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 4/4] drm/i915: Program vactive & hactive display size for both ports

[Ville Syrjälä]

On Wed, Sep 16, 2015 at 02:48:41PM +0530, Gaurav K Singh wrote:
> Program the required mmio regs for hactive and vactive display size.

This doesn't program anything, just reads them out.

As for readout, do the pipe registers contain the same values? In that
case we could just do a sanity check to make sure the DSI and pipe
registers match.

> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   37 ++++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ab9f06a..0285af9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7653,6 +7653,7 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> +	bool is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
>  	uint32_t tmp;
>  
>  	tmp = I915_READ(HTOTAL(cpu_transcoder));
> @@ -7681,6 +7682,25 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
>  		pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
>  	}
>  
> +	 if (IS_BROXTON(dev) && is_dsi) {
> +		struct intel_encoder *encoder;
> +
> +		for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
> +			struct intel_dsi *intel_dsi =
> +				enc_to_intel_dsi(&encoder->base);
> +			enum port port;
> +
> +			for_each_dsi_port(port, intel_dsi->ports) {
> +				pipe_config->base.adjusted_mode.crtc_hdisplay =
> +						I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
> +				pipe_config->base.adjusted_mode.crtc_vdisplay =
> +						I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
> +				pipe_config->base.adjusted_mode.crtc_vtotal =
> +						I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
> +			}
> +		}
> +	}
> +
>  	tmp = I915_READ(PIPESRC(crtc->pipe));
>  	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
>  	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
> @@ -10569,6 +10589,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
>  	int vtot = I915_READ(VTOTAL(cpu_transcoder));
>  	int vsync = I915_READ(VSYNC(cpu_transcoder));
>  	enum pipe pipe = intel_crtc->pipe;
> +	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>  
>  	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
>  	if (!mode)
> @@ -10598,6 +10619,22 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
>  	mode->vsync_start = (vsync & 0xffff) + 1;
>  	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
>  
> +	if (IS_BROXTON(dev) && is_dsi) {
> +		struct intel_encoder *encoder;
> +
> +		for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
> +			struct intel_dsi *intel_dsi =
> +						enc_to_intel_dsi(&encoder->base);
> +			enum port port;
> +
> +			for_each_dsi_port(port, intel_dsi->ports) {
> +				mode->vtotal = I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
> +				mode->hdisplay = I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
> +				mode->vdisplay = I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
> +			}
> +		}
> +	}
> +
>  	drm_mode_set_name(mode);
>  
>  	return mode;
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 0/4] DSI Dual link enabling on BXT

[Ville Syrjälä]

On Wed, Sep 16, 2015 at 02:48:37PM +0530, Gaurav K Singh wrote:
> Hi,
> 
> These patches enable DSI dual link mode on BXT boards. These set of patches
> build on top of the floated DSI Video mode patches on BXT (Uma's patches).

BTW I posted a few DSI related patch. Maybe you can take a look?

http://lists.freedesktop.org/archives/intel-gfx/2015-September/075097.html
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075568.html

> 
> Regards
> Gaurav
> 
> Gaurav K Singh (4):
>   drm/i915: Enable dual link mode in BXT
>   drm/i915: Use adjusted mode clk for calculating DSI clk
>   drm/i915: Execute RESET sequence before device ready
>   drm/i915: Program vactive & hactive display size for both ports
> 
>  drivers/gpu/drm/i915/i915_reg.h            |    7 +++---
>  drivers/gpu/drm/i915/intel_display.c       |   37 ++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dsi.c           |   11 ++++++---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   15 +++++++++++
>  drivers/gpu/drm/i915/intel_dsi_pll.c       |    4 ++-
>  include/drm/drm_panel.h                    |    9 +++++++
>  6 files changed, 76 insertions(+), 7 deletions(-)
> 
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 0/4] DSI Dual link enabling on BXT

[Singh, Gaurav K]

On 9/16/2015 2:48 PM, Gaurav K Singh wrote:
> Hi,
>
> These patches enable DSI dual link mode on BXT boards. These set of patches
> build on top of the floated DSI Video mode patches on BXT (Uma's patches).
>
> Regards
> Gaurav
>
> Gaurav K Singh (4):
>    drm/i915: Enable dual link mode in BXT
>    drm/i915: Use adjusted mode clk for calculating DSI clk
>    drm/i915: Execute RESET sequence before device ready
>    drm/i915: Program vactive & hactive display size for both ports
>
>   drivers/gpu/drm/i915/i915_reg.h            |    7 +++---
>   drivers/gpu/drm/i915/intel_display.c       |   37 ++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_dsi.c           |   11 ++++++---
>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   15 +++++++++++
>   drivers/gpu/drm/i915/intel_dsi_pll.c       |    4 ++-
>   include/drm/drm_panel.h                    |    9 +++++++
>   6 files changed, 76 insertions(+), 7 deletions(-)
>
Hi All,

Did anyone get a chance to review this patchset.

With regards,
Gaurav


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Re: [PATCH 0/4] DSI Dual link enabling on BXT

[Jani Nikula]

On Wed, 23 Sep 2015, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
> On 9/16/2015 2:48 PM, Gaurav K Singh wrote:
>> Hi,
>>
>> These patches enable DSI dual link mode on BXT boards. These set of patches
>> build on top of the floated DSI Video mode patches on BXT (Uma's patches).
>>
>> Regards
>> Gaurav
>>
>> Gaurav K Singh (4):
>>    drm/i915: Enable dual link mode in BXT
>>    drm/i915: Use adjusted mode clk for calculating DSI clk
>>    drm/i915: Execute RESET sequence before device ready
>>    drm/i915: Program vactive & hactive display size for both ports
>>
>>   drivers/gpu/drm/i915/i915_reg.h            |    7 +++---
>>   drivers/gpu/drm/i915/intel_display.c       |   37 ++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_dsi.c           |   11 ++++++---
>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   15 +++++++++++
>>   drivers/gpu/drm/i915/intel_dsi_pll.c       |    4 ++-
>>   include/drm/drm_panel.h                    |    9 +++++++
>>   6 files changed, 76 insertions(+), 7 deletions(-)
>>
> Hi All,
>
> Did anyone get a chance to review this patchset.

Looking at some old patches... there's review from Ville to address
specific issues, please look into them.

BR,
Jani.


>
> With regards,
> Gaurav
>
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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