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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work
Date: Tue, 22 Sep 2015 20:41:18 +0300	[thread overview]
Message-ID: <20150922174118.GU26517@intel.com> (raw)
In-Reply-To: <1442595836-23981-1-git-send-email-ville.syrjala@linux.intel.com>

On Fri, Sep 18, 2015 at 08:03:13PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Inspired by the recent misplaced parenthesis fix from Damien, I decided to try
> and see what it would take to make our register access type safe. By that mean
> you shouldn't be able to pass in anything by a proper register offset in. After
> a couple of days of hacking, this series is the result.
> 
> I managed to split out all the cleanup stuff upfront, but there is quite a bit
> of it. I did include a few random patches no strictly needed, but as long as I
> was going through the register macros I tried to fix whatever was wrong.
> 
> The actual type safe stuff is in the last patch, and I'm posting that on as an
> RFC to see what other people think about the idea. I think most of the prep
> work would be nice to have even if we decide against the type safety. Oh, turns
> out I couldn't find any new "passing crap as the register offset" type of bugs
> with this work, but this would prevent them from sneaking in. As mentioned in
> the patch, I limited this only for mmio regs for now, but we could expand it
> cover other register types.
> 
> I've only smoke tested this on IVB, HSW and BSW.
> 
> The whole thing is available in my git repo:
> git://github.com/vsyrjala/linux.git type_safe_reg_access_3

FYI I've pushed a more polished version
git://github.com/vsyrjala/linux.git type_safe_reg_access_4

I think I'll refrain from posting the extra patches (managed to accumulate
quite a few more) quite so soon to avoid too much flooding. But I figured
I'll give people a heads up in case someone is intersted what the (hopefully)
final version would look like.

> 
> Ville Syrjälä (43):
>   drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc,i2c}_bus()
>   drm/i915: Parametrize LRC registers
>   drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS
>   drm/i915: Parametrize fence registers
>   drm/i915: Parametrize FBC_TAG registers
>   drm/i915: Parametrize ILK turbo registers
>   drm/i915: Replace raw numbers with the approproate register name in
>     ILK turbo code
>   drm/i915: Parametrize TV luma/chroma filter registers
>   drm/i915: Parametrize DDI_BUF_TRANS registers
>   drm/i915: Parametrize CSR_PROGRAM registers
>   drm/i915: Parametrize UOS_RSA_SCRATCH
>   drm/i915: Add LO/HI PRIVATE_PAT registers
>   drm/i915: Always use GEN8_RING_PDP_{LDW,UDW} instead of hand rolling
>     the register offsets
>   drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR
>   drm/i915: Parametrize PALETTE and LGC_PALETTE
>   drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/
>   drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/
>   drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/
>   drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.
>   drm/i915: Use paramtrized WRPLL_CTL()
>   drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE
>   drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/
>   drm/i915: Eliminate weird parameter inversion from BXT PPS registers
>   drm/i915: Parametrize HSW video DIP data registers
>   drm/i915: Include gpio_mmio_base in GMBUS reg defines
>   drm/i915: Protect register macro arguments
>   drm/i915: Fix a few bad hex numbers in register defines
>   drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function
>   drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.
>   drm/i915: Parametrize and fix SWF registers
>   drm/i915: Throw out some useless variables
>   drm/i915: Clean up LVDS register handling
>   drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE
>   drm/i915: Turn __raw_i915_read8() & co. in to inline functions
>   drm/i915: Move __raw_i915_read8() & co. into i915_drv.h
>   drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
>   drm/i915: Replace the aux ddc name switch statement with a table
>   drm/i915: Parametrize AUX registes
>   drm/i915: Add dev_priv->psr_mmio_base
>   drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]
>   drm/i915: Model PSR AUX register selection more like the normal AUX
>     code
>   drm/i915: Prefix raw register defines with underscore
>   WIP: drm/i915: Type safe register read/write
> 
>  drivers/gpu/drm/i915/dvo.h                 |    2 +-
>  drivers/gpu/drm/i915/i915_cmd_parser.c     |   17 +-
>  drivers/gpu/drm/i915/i915_debugfs.c        |   26 +-
>  drivers/gpu/drm/i915/i915_drv.c            |    8 +-
>  drivers/gpu/drm/i915/i915_drv.h            |   66 +-
>  drivers/gpu/drm/i915/i915_gem_context.c    |    4 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |    2 +-
>  drivers/gpu/drm/i915/i915_gem_fence.c      |   41 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c        |   35 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c      |   25 +-
>  drivers/gpu/drm/i915/i915_guc_reg.h        |   50 +-
>  drivers/gpu/drm/i915/i915_guc_submission.c |    2 +-
>  drivers/gpu/drm/i915/i915_irq.c            |   68 +-
>  drivers/gpu/drm/i915/i915_reg.h            | 2768 ++++++++++++++--------------
>  drivers/gpu/drm/i915/i915_suspend.c        |   45 +-
>  drivers/gpu/drm/i915/i915_sysfs.c          |    6 +-
>  drivers/gpu/drm/i915/i915_trace.h          |    4 +-
>  drivers/gpu/drm/i915/i915_vgpu.c           |    6 +-
>  drivers/gpu/drm/i915/i915_vgpu.h           |    2 +-
>  drivers/gpu/drm/i915/intel_audio.c         |   14 +-
>  drivers/gpu/drm/i915/intel_crt.c           |   16 +-
>  drivers/gpu/drm/i915/intel_csr.c           |   17 +-
>  drivers/gpu/drm/i915/intel_ddi.c           |  117 +-
>  drivers/gpu/drm/i915/intel_display.c       |  260 ++-
>  drivers/gpu/drm/i915/intel_dp.c            |  220 ++-
>  drivers/gpu/drm/i915/intel_drv.h           |   14 +-
>  drivers/gpu/drm/i915/intel_dsi.c           |    9 +-
>  drivers/gpu/drm/i915/intel_dvo.c           |   14 +-
>  drivers/gpu/drm/i915/intel_fbc.c           |    2 +-
>  drivers/gpu/drm/i915/intel_fifo_underrun.c |    4 +-
>  drivers/gpu/drm/i915/intel_guc_loader.c    |    2 +-
>  drivers/gpu/drm/i915/intel_hdmi.c          |   71 +-
>  drivers/gpu/drm/i915/intel_i2c.c           |   64 +-
>  drivers/gpu/drm/i915/intel_lrc.c           |   52 +-
>  drivers/gpu/drm/i915/intel_lrc.h           |   10 -
>  drivers/gpu/drm/i915/intel_lvds.c          |   36 +-
>  drivers/gpu/drm/i915/intel_pm.c            |   29 +-
>  drivers/gpu/drm/i915/intel_psr.c           |   63 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c    |   15 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.h    |    2 +-
>  drivers/gpu/drm/i915/intel_sdvo.c          |   23 +-
>  drivers/gpu/drm/i915/intel_tv.c            |    8 +-
>  drivers/gpu/drm/i915/intel_uncore.c        |  133 +-
>  drivers/pci/quirks.c                       |    8 +-
>  44 files changed, 2189 insertions(+), 2191 deletions(-)
> 
> -- 
> 2.4.6

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2015-09-22 17:41 UTC|newest]

Thread overview: 136+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-18 17:03 [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work ville.syrjala
2015-09-18 17:03 ` [PATCH 01/43] drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc, i2c}_bus() ville.syrjala
2015-09-21  7:34   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 02/43] drm/i915: Parametrize LRC registers ville.syrjala
2015-09-21  7:36   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 03/43] drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS ville.syrjala
2015-09-21  7:37   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 04/43] drm/i915: Parametrize fence registers ville.syrjala
2015-09-21  7:45   ` Jani Nikula
2015-09-21 12:33     ` Ville Syrjälä
2015-09-21 13:07       ` Ville Syrjälä
2015-09-21 15:05   ` [PATCH v2 " ville.syrjala
2015-09-25 12:02     ` Jani Nikula
2015-09-28  8:31       ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 05/43] drm/i915: Parametrize FBC_TAG registers ville.syrjala
2015-09-21  7:46   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 06/43] drm/i915: Parametrize ILK turbo registers ville.syrjala
2015-09-21  7:47   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 07/43] drm/i915: Replace raw numbers with the approproate register name in ILK turbo code ville.syrjala
2015-09-21  7:48   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 08/43] drm/i915: Parametrize TV luma/chroma filter registers ville.syrjala
2015-09-21  7:50   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 09/43] drm/i915: Parametrize DDI_BUF_TRANS registers ville.syrjala
2015-09-21  7:59   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 10/43] drm/i915: Parametrize CSR_PROGRAM registers ville.syrjala
2015-09-23 14:15   ` Mika Kuoppala
2015-09-23 15:17     ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 11/43] drm/i915: Parametrize UOS_RSA_SCRATCH ville.syrjala
2015-09-28 11:39   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 12/43] drm/i915: Add LO/HI PRIVATE_PAT registers ville.syrjala
2015-09-28 11:40   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 13/43] drm/i915: Always use GEN8_RING_PDP_{LDW, UDW} instead of hand rolling the register offsets ville.syrjala
2015-09-28 11:42   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 14/43] drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR ville.syrjala
2015-09-28 11:44   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 15/43] drm/i915: Parametrize PALETTE and LGC_PALETTE ville.syrjala
2015-09-28 11:45   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/ ville.syrjala
2015-09-22 16:47   ` [PATCH v2 " ville.syrjala
2015-09-28 11:50     ` Jani Nikula
2015-09-28 13:35       ` Daniel Vetter
2015-09-28 11:49   ` [PATCH " Jani Nikula
2015-09-18 17:03 ` [PATCH 17/43] drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/ ville.syrjala
2015-09-29 14:14   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 18/43] drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/ ville.syrjala
2015-09-29 14:16   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc ville.syrjala
2015-09-30 13:44   ` Jani Nikula
2015-09-30 13:53     ` Ville Syrjälä
2015-09-30 14:06   ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 20/43] drm/i915: Use paramtrized WRPLL_CTL() ville.syrjala
2015-09-30 13:58   ` Jani Nikula
2015-09-30 14:00     ` Ville Syrjälä
2015-10-26 14:49     ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 21/43] drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE ville.syrjala
2015-09-28 11:53   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 22/43] drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/ ville.syrjala
2015-09-28 11:53   ` Jani Nikula
2015-09-28 13:38     ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 23/43] drm/i915: Eliminate weird parameter inversion from BXT PPS registers ville.syrjala
2015-10-12 16:41   ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 24/43] drm/i915: Parametrize HSW video DIP data registers ville.syrjala
2015-10-12 15:54   ` Jesse Barnes
2015-10-12 16:15     ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines ville.syrjala
2015-10-12 15:56   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 26/43] drm/i915: Protect register macro arguments ville.syrjala
2015-10-12 16:03   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 27/43] drm/i915: Fix a few bad hex numbers in register defines ville.syrjala
2015-10-12 16:04   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 28/43] drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function ville.syrjala
2015-10-12 16:05   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 29/43] drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc ville.syrjala
2015-10-12 16:06   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 30/43] drm/i915: Parametrize and fix SWF registers ville.syrjala
2015-10-12 16:07   ` Jesse Barnes
2015-10-12 16:17     ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 31/43] drm/i915: Throw out some useless variables ville.syrjala
2015-09-22 16:50   ` [PATCH v2 " ville.syrjala
2015-10-12 16:09     ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 32/43] drm/i915: Clean up LVDS register handling ville.syrjala
2015-10-12 16:09   ` Jesse Barnes
2015-11-01 15:33   ` Lukas Wunner
2015-11-04 16:59     ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 33/43] drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE ville.syrjala
2015-10-12 16:12   ` Jesse Barnes
2015-10-13 11:21     ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 34/43] drm/i915: Turn __raw_i915_read8() & co. in to inline functions ville.syrjala
2015-09-18 17:03 ` [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h ville.syrjala
2015-09-18 17:42   ` Chris Wilson
2015-09-18 18:23     ` Ville Syrjälä
2015-09-18 18:33       ` Chris Wilson
2015-09-18 18:37         ` Ville Syrjälä
2015-09-18 18:44           ` Chris Wilson
2015-09-18 19:26             ` Ville Syrjälä
2015-09-21 16:26               ` Jesse Barnes
2015-09-21 16:53                 ` Ville Syrjälä
2015-09-21 16:57                   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 36/43] drm/i915: Remove the magic AUX_CTL is at DP + foo tricks ville.syrjala
2015-09-18 17:03 ` [PATCH 37/43] drm/i915: Replace the aux ddc name switch statement with a table ville.syrjala
2015-09-18 17:03 ` [PATCH 38/43] drm/i915: Parametrize AUX registes ville.syrjala
2015-09-28 12:15   ` Jani Nikula
2015-09-28 13:28     ` Daniel Vetter
2015-09-28 13:34       ` Ville Syrjälä
2015-09-28 13:52         ` Daniel Vetter
2015-09-28 13:57           ` Jani Nikula
2015-09-28 15:09   ` [PATCH v2 38/43] drm/i915: Parametrize AUX registers ville.syrjala
2015-10-20 13:05     ` Jani Nikula
2015-10-20 13:37       ` Ville Syrjälä
2015-10-20 14:00     ` [PATCH v3 " ville.syrjala
2015-10-21  7:08       ` Jani Nikula
2015-09-18 17:03 ` [PATCH 39/43] drm/i915: Add dev_priv->psr_mmio_base ville.syrjala
2015-10-20 13:08   ` Jani Nikula
2015-10-20 14:01   ` [PATCH v2 " ville.syrjala
2015-10-21  7:09     ` Jani Nikula
2015-09-18 17:03 ` [PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[] ville.syrjala
2015-09-28 12:28   ` Jani Nikula
2015-09-28 14:36     ` Ville Syrjälä
2015-09-28 15:10   ` [PATCH v2 " ville.syrjala
2015-10-20 14:02     ` [PATCH v3 " ville.syrjala
2015-09-18 17:03 ` [PATCH 41/43] drm/i915: Model PSR AUX register selection more like the normal AUX code ville.syrjala
2015-09-28 15:11   ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 42/43] drm/i915: Prefix raw register defines with underscore ville.syrjala
2015-09-18 17:03 ` [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write ville.syrjala
2015-09-18 17:33   ` Chris Wilson
2015-09-18 17:43     ` Ville Syrjälä
2015-09-18 18:12       ` Chris Wilson
2015-09-18 18:34         ` Ville Syrjälä
2015-09-23 15:23   ` Daniel Vetter
2015-09-24 15:38     ` Ville Syrjälä
2015-09-28 12:56       ` Jani Nikula
2015-09-28 13:03         ` Ville Syrjälä
2015-09-28 13:52           ` Daniel Vetter
2015-09-18 18:17 ` [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work Chris Wilson
2015-09-22 17:41 ` Ville Syrjälä [this message]
2015-10-28 12:55 ` Jani Nikula

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