From: Daniel Vetter <daniel@ffwll.ch>
To: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Akash Goel <akash.goel@intel.com>
Subject: Re: [PATCH v2 4/7] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating
Date: Wed, 23 Sep 2015 10:51:55 +0200 [thread overview]
Message-ID: <20150923085155.GW3383@phenom.ffwll.local> (raw)
In-Reply-To: <1442033276-2191-5-git-send-email-sagar.a.kamble@intel.com>
On Sat, Sep 12, 2015 at 10:17:53AM +0530, Sagar Arun Kamble wrote:
> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6e4818d..4d6bb6b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4830,7 +4830,13 @@ static void gen9_enable_rc6(struct drm_device *dev)
> I915_WRITE(GEN6_RC_CONTROL, 0);
>
> /* 2b: Program RC6 thresholds.*/
> - I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> +
> + /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
> + if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
> + (INTEL_REVID(dev) <= SKL_REVID_E0)))
Same deal again.
-Daniel
> + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> + else
> + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_ring(ring, dev_priv, unused)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2015-09-23 8:49 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-12 4:47 [PATCH v2 0/7] Gen9 RC6, Turbo, Coarse Power Gating Fixes Sagar Arun Kamble
2015-09-12 4:47 ` [PATCH v2 1/7] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro Sagar Arun Kamble
2015-09-21 18:49 ` Yu Dai
2015-09-12 4:47 ` [PATCH v2 2/7] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
2015-09-21 18:49 ` Yu Dai
2015-09-23 8:49 ` Daniel Vetter
2015-09-12 4:47 ` [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode Sagar Arun Kamble
2015-09-21 18:49 ` Yu Dai
2015-09-21 21:47 ` O'Rourke, Tom
2015-09-23 8:50 ` Daniel Vetter
2015-09-23 9:33 ` Kamble, Sagar A
2015-09-23 9:36 ` [PATCH 1/1] drm/i915: Update Promotion timer for RC6 TO Mode Sagar Arun Kamble
2015-09-24 21:11 ` O'Rourke, Tom
2015-09-30 10:43 ` [PATCH v2 " Sagar Arun Kamble
2015-09-30 16:38 ` O'Rourke, Tom
2015-10-01 8:21 ` Daniel Vetter
2015-09-12 4:47 ` [PATCH v2 4/7] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating Sagar Arun Kamble
2015-09-21 18:50 ` Yu Dai
2015-09-23 8:51 ` Daniel Vetter [this message]
2015-09-12 4:47 ` [PATCH v2 5/7] drm/i915: Program GuC MAX IDLE Count Sagar Arun Kamble
2015-09-21 18:50 ` Yu Dai
2015-09-12 4:47 ` [PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly Sagar Arun Kamble
2015-09-21 16:51 ` Yu Dai
2015-09-22 22:51 ` Yu Dai
2015-09-21 18:59 ` Yu Dai
2015-09-12 4:47 ` [PATCH v2 7/7] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
2015-09-21 11:24 ` [PATCH v3 1/1] " Sagar Arun Kamble
2015-09-21 18:50 ` [PATCH v2 7/7] " Yu Dai
2015-09-23 6:32 ` Kamble, Sagar A
2015-09-23 8:53 ` Daniel Vetter
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