From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/7] drm/i915/gen8: Move GEN8_ROW_CHICKEN WA to common init fn
Date: Fri, 25 Sep 2015 17:18:53 +0300 [thread overview]
Message-ID: <20150925141853.GU26517@intel.com> (raw)
In-Reply-To: <1443187414-963-5-git-send-email-arun.siluvery@linux.intel.com>
On Fri, Sep 25, 2015 at 02:23:32PM +0100, Arun Siluvery wrote:
> Move WaDisablePartialInstShootdown and WaDisableThreadStallDopClockGating
NAK for WaDisableThreadStallDopClockGating, we don't want it on production BDW.
Should just kill it for BDW instead.
>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++++------------
> 1 file changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a06788a..5d15e31 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -807,6 +807,12 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
>
> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>
> + /* WaDisablePartialInstShootdown:bdw,chv */
> + /* WaDisableThreadStallDopClockGating:chv, bdw (pre-production) */
> + WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> + PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> + STALL_DOP_GATING_DISABLE);
> +
> /* WaDisableAsyncFlipPerfMode:bdw,chv */
> WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
>
> @@ -826,12 +832,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> if (ret)
> return ret;
>
> - /* WaDisablePartialInstShootdown:bdw */
> - /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> - WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> - PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> - STALL_DOP_GATING_DISABLE);
> -
> /* WaDisableDopClockGating:bdw */
> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
> @@ -888,12 +888,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> if (ret)
> return ret;
>
> - /* WaDisablePartialInstShootdown:chv */
> - /* WaDisableThreadStallDopClockGating:chv */
> - WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> - PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> - STALL_DOP_GATING_DISABLE);
> -
> /* Use Force Non-Coherent whenever executing a 3D context. This is a
> * workaround for a possible hang in the unlikely event a TLB
> * invalidation occurs during a PSD flush.
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-09-25 14:18 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-25 13:23 [PATCH 1/7] drm/i915/gen8: Add gen8_init_workarounds for common WA Arun Siluvery
2015-09-25 13:23 ` [PATCH 2/7] drm/i915/gen8: Move INSTPM WA to common function Arun Siluvery
2015-09-25 13:23 ` [PATCH 3/7] drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn Arun Siluvery
2015-09-25 13:23 ` [PATCH 4/7] drm/i915/gen8: Move Wa4x4STCOptimizationDisable " Arun Siluvery
2015-09-25 13:23 ` [PATCH 5/7] drm/i915/gen8: Move GEN8_ROW_CHICKEN WA " Arun Siluvery
2015-09-25 14:18 ` Ville Syrjälä [this message]
2015-09-25 13:23 ` [PATCH 6/7] drm/i915/gen8: Move GEN7_GT_MODE " Arun Siluvery
2015-09-25 13:23 ` [PATCH 7/7] drm/i915/gen8: Move HiZ RAW stall optimization disable " Arun Siluvery
2015-09-25 14:28 ` Ville Syrjälä
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