Re: [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, Sep 25, 2015 at 05:40:46PM +0100, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Series lgtm, so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1e60aa0..35afe73 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -819,7 +819,9 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
>  	 * invalidation occurs during a PSD flush.
>  	 */
>  	/* WaForceEnableNonCoherent:bdw,chv */
> +	/* WaHdcDisableFetchWhenMasked:bdw,chv */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
> +			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
>  			  HDC_FORCE_NON_COHERENT);
>  
>  	/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
> @@ -870,8 +872,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  /* WaForceContextSaveRestoreNonCoherent:bdw */
>  			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> -			  /* WaHdcDisableFetchWhenMasked:bdw */
> -			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
>  			  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
>  			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>  
> @@ -891,10 +891,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  	/* WaDisableThreadStallDopClockGating:chv */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
>  
> -	/* WaHdcDisableFetchWhenMasked:chv */
> -	WA_SET_BIT_MASKED(HDC_CHICKEN0,
> -			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
> -
>  	/* Improve HiZ throughput on CHV. */
>  	WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
>  
> -- 
> 1.9.1

-- 
Ville Syrjälä
Intel OTC
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