Re: [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Sep 28, 2015 at 04:51:52PM +0100, Arun Siluvery wrote:
> On 25/09/2015 18:09, Ville Syrjälä wrote:
> > On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote:
> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> >>   1 file changed, 4 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> index ab5ac5e..093a5e4 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
> >>   	/* WaDisableKillLogic:bxt,skl */
> >>   	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> >>   		   ECOCHK_DIS_TLB);
> >> +
> >> +	/* WaOCLCoherentLineFlush:skl,bxt */
> >> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> >> +				    GEN8_LQSC_FLUSH_COHERENT_LINES));
> >
> > According to Bspec + w/a db this should be done for BDW too (actually
> > BSpec shows it for BDW only?). If that's the case, then we should be
> > able to kill gen8_emit_flush_coherentl3_wa(), no? Well, as long as
> > someone goes and adds the DC flush to the normal post batch flush.
> >
> Yes this is applicable for BDW also but I wanted to keep only Gen9 
> patches in this series. I will send separate patch for BDW.
> We would still need gen8_emit_flush_coherentl3_wa() because WA requires 
> that the flush need to happen from the WA batch itself during context 
> switch.

If we already flush all coherent lines out from DC after each batch,
how can there still be coherent lines in the DC on a context switch?

But spelling that out made me think that mid-batch preemption would
still need it I suppose. But w/o preemption I see no reason why it
would be needed.

-- 
Ville Syrjälä
Intel OTC
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