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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Konduru, Chandra" <chandra.konduru@intel.com>
Cc: "Vetter, Daniel" <daniel.vetter@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Syrjala, Ville" <ville.syrjala@intel.com>
Subject: Re: [PATCH 09/15] drm/i915: Add NV12 support to intel_framebuffer_init
Date: Thu, 1 Oct 2015 14:41:06 +0300	[thread overview]
Message-ID: <20151001114106.GC26517@intel.com> (raw)
In-Reply-To: <20151001113727.GB26517@intel.com>

On Thu, Oct 01, 2015 at 02:37:27PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 30, 2015 at 10:58:07PM +0000, Konduru, Chandra wrote:
> > > > @@ -14241,6 +14241,7 @@ static int intel_framebuffer_init(struct
> > > drm_device *dev,
> > > >  {
> > > >  	unsigned int aligned_height;
> > > >  	int ret;
> > > > +	int i;
> > > >  	u32 pitch_limit, stride_alignment;
> > > >
> > > >  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> > > > @@ -14255,7 +14256,8 @@ static int intel_framebuffer_init(struct
> > > drm_device *dev,
> > > >  		}
> > > >  	} else {
> > > >  		if (obj->tiling_mode == I915_TILING_X)
> > > > -			mode_cmd->modifier[0] =
> > > I915_FORMAT_MOD_X_TILED;
> > > > +			for (i = 0; i < drm_format_num_planes(mode_cmd-
> > > >pixel_format); i++)
> > > > +				mode_cmd->modifier[i] =
> > > I915_FORMAT_MOD_X_TILED;
> > > 
> > > The other branch needs updating too so that it will reject the operation
> > > if the modifier disagrees with the obj tiling mode.
> > 
> > Is below something you meant?
> > 
> > @@ -14223,10 +14223,12 @@ static int intel_framebuffer_init(struct drm_device *d
> >         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
> >                 /* Enforce that fb modifier and tiling mode match, but only for
> >                  * X-tiled. This is needed for FBC. */
> > -               if (!!(obj->tiling_mode == I915_TILING_X) !=
> > -                   !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
> > -                       DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
> > -                       return -EINVAL;
> > +               for (i = 0; i < drm_format_num_planes(mode_cmd->pixel_format); i
> > +                       if (!!(obj->tiling_mode == I915_TILING_X) !=
> > +                       !!(mode_cmd->modifier[i] == I915_FORMAT_MOD_X_TILED)) {
> > +                               DRM_DEBUG("tiling_mode doesn't match fb modifier
> > +                               return -EINVAL;
> > +                       }
> >                 }
> 
> Yep.
> 
> >         } else {
> > 
> > > > +		if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED
> > > &&
> > > > +			(mode_cmd->offsets[1] & 0xFFF)) {
> > > 
> > > I've been trying to solicit ideas on how we should define the offsets[];
> > > raw byte offset, or linear offset. I didn't get many opinions yet. So we
> > > need to figure it out and document it somewhere before we expose it to
> > > the world. In the meantime we could just reject non tile row aligned
> > > offsets regardless of the tiling mode.
> > 
> > Above check is simply making sure tile Yf, uv offset starts on a new page. 
> > Is there any issue with above check?
> 
> It won't necessarily be a page boundary if we interpret offsets[] as a linear
> offset.
> 
> Eg. let's assume 4x4 tile size, stride=8, and offset=16. If interpret
> the offset as a linear offset we would land at 'x', but interpreted as
> a raw byte offset (not sure that's a good name, maybe untiled offset?)
> we'd land at 'y'.
> 
> -----------
> |    |y   |
> |    |    |
> |x   |    |
> |    |    |
> -----------
> |z   |    |
> |    |    |
> |    |    |
> |    |    |
> -----------
> 
> If we had offset=32, then of course we would land at 'z' for both cases,
> which is why I suggested that if we haven't made up our mind about what
> offsets[] is, we could require it to be tile row aligned so that there
> would be no difference between the two interpretations.

Oh and I just figured out that linear offset would probably be better
because that also isolates us from having to think about the internal
tile layout, as in which way the bytes/owords/whatver are walked within
the tile.

-- 
Ville Syrjälä
Intel OTC
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  reply	other threads:[~2015-10-01 11:41 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-05  2:32 [PATCH 00/15] drm/i915: Adding NV12 for skylake display Chandra Konduru
2015-09-05  2:32 ` [PATCH 01/15] drm/i915: Allocate min dbuf blocks per bspec Chandra Konduru
2015-09-29 17:45   ` Ville Syrjälä
2015-09-30 12:20     ` Daniel Vetter
2015-09-05  2:32 ` [PATCH 02/15] drm/i915: In DBUF/WM calcs for 90/270, swap w & h Chandra Konduru
2015-09-29 17:46   ` Ville Syrjälä
2015-09-05  2:32 ` [PATCH 03/15] drm/i915: Set scaler mode for NV12 Chandra Konduru
2015-09-29 17:47   ` Ville Syrjälä
2015-09-30 12:22     ` Daniel Vetter
2015-09-30 15:18       ` Daniel Vetter
2015-09-05  2:33 ` [PATCH 04/15] drm/i915: Stage scaler request for NV12 as src format Chandra Konduru
2015-09-10 17:36   ` Ville Syrjälä
2015-09-10 19:00     ` Konduru, Chandra
2015-09-11 16:43   ` Chandra Konduru
2015-09-05  2:33 ` [PATCH 05/15] drm/i915: Update format_is_yuv() to include NV12 Chandra Konduru
2015-09-29 17:47   ` Ville Syrjälä
2015-09-05  2:33 ` [PATCH 06/15] drm/i915: Upscale scaler max scale for NV12 Chandra Konduru
2015-09-29 17:48   ` Ville Syrjälä
2015-09-05  2:33 ` [PATCH 07/15] drm/i915: Add NV12 as supported format for primary plane Chandra Konduru
2015-09-10 17:40   ` Ville Syrjälä
2015-09-10 21:06     ` Konduru, Chandra
2015-09-10 21:28       ` Ville Syrjälä
2015-09-10 22:00         ` Konduru, Chandra
2015-09-14  8:43         ` Daniel Vetter
2015-09-16  1:34           ` Konduru, Chandra
2015-09-11 16:43   ` Chandra Konduru
2015-09-29 18:47     ` Ville Syrjälä
2015-09-05  2:33 ` [PATCH 08/15] drm/i915: Add NV12 as supported format for sprite plane Chandra Konduru
2015-09-29 17:50   ` Ville Syrjälä
2015-09-29 19:00     ` Ville Syrjälä
2015-09-05  2:33 ` [PATCH 09/15] drm/i915: Add NV12 support to intel_framebuffer_init Chandra Konduru
2015-09-09 22:59   ` Chandra Konduru
2015-09-10 18:34     ` Ville Syrjälä
2015-09-10 19:14       ` Konduru, Chandra
2015-09-10 19:43         ` Ville Syrjälä
2015-09-10 20:45           ` Konduru, Chandra
2015-09-14  8:45             ` Daniel Vetter
2015-09-16  1:35               ` Konduru, Chandra
2015-09-10 19:46       ` Ville Syrjälä
2015-09-10 20:59         ` Konduru, Chandra
     [not found]         ` <76A9B330A4D78C4D99CB292C4CC06C0E370D47CC@fmsmsx101.amr.corp.intel.com>
2015-09-21 16:14           ` Konduru, Chandra
2015-09-11 16:44   ` Chandra Konduru
2015-09-29 18:58     ` Ville Syrjälä
2015-09-30 22:58       ` Konduru, Chandra
2015-10-01 11:37         ` Ville Syrjälä
2015-10-01 11:41           ` Ville Syrjälä [this message]
2015-10-01 18:36             ` Konduru, Chandra
2015-09-05  2:33 ` [PATCH 10/15] drm/i915: Add NV12 to primary plane programming Chandra Konduru
2015-09-05  2:33 ` [PATCH 11/15] drm/i915: Add NV12 to sprite " Chandra Konduru
2015-09-05  2:33 ` [PATCH 12/15] drm/i915: Set initial phase & trip for NV12 scaler Chandra Konduru
2015-09-29 18:37   ` Ville Syrjälä
2015-09-05  2:33 ` [PATCH 13/15] drm/i915: skl nv12 wa - disable streamer fix Chandra Konduru
2015-09-05  2:33 ` [PATCH 14/15] drm/i915: skl nv12 wa - NV12 to RGB switch Chandra Konduru
2015-09-09 23:00   ` Chandra Konduru
2015-09-05  2:33 ` [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format Chandra Konduru

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