From: Daniel Vetter <daniel@ffwll.ch>
To: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 1/1] drm/i915: Update Promotion timer for RC6 TO Mode
Date: Thu, 1 Oct 2015 15:18:25 +0200 [thread overview]
Message-ID: <20151001131825.GZ3383@phenom.ffwll.local> (raw)
In-Reply-To: <1443693464-5581-1-git-send-email-sagar.a.kamble@intel.com>
On Thu, Oct 01, 2015 at 03:27:44PM +0530, Sagar Arun Kamble wrote:
> When using RC6 timeout mode, the timeout value
> should be written to GEN6_RC6_THRESHOLD.
>
> v2: Updated commit message. (Tom)
>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
When resending a patch which already has an r-b and you don't add that
nore Cc: the reviewer then that just wastes people time. Also this patch
should have a "v3: Rebase over whitespace differences" line.
Please retry, thanks.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c98eee6..c16f496 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4791,7 +4791,6 @@ static void gen9_enable_rc6(struct drm_device *dev)
> I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
>
> I915_WRITE(GEN6_RC_SLEEP, 0);
> - I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>
> /* 2c: Program Coarse Power Gating Policies. */
> I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> @@ -4802,16 +4801,19 @@ static void gen9_enable_rc6(struct drm_device *dev)
> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> "on" : "off");
> -
> + /* WaRsUseTimeoutMode */
> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
> + I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
> I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> GEN7_RC_CTL_TO_MODE |
> rc6_mask);
> - else
> + } else {
> + I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
> I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> GEN6_RC_CTL_EI_MODE(1) |
> rc6_mask);
> + }
>
> /*
> * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Intel-gfx mailing list
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next prev parent reply other threads:[~2015-10-01 13:15 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <f2d2fe95072acd5404f8051b8bf1195c61a47fb5>
2015-10-01 9:57 ` [PATCH v2 1/1] drm/i915: Update Promotion timer for RC6 TO Mode Sagar Arun Kamble
2015-10-01 13:18 ` Daniel Vetter [this message]
2015-10-01 14:59 ` [PATCH v3 " Sagar Arun Kamble
2015-10-05 16:29 ` O'Rourke, Tom
2015-09-24 21:11 [PATCH " O'Rourke, Tom
2015-09-30 10:43 ` [PATCH v2 " Sagar Arun Kamble
2015-09-30 16:38 ` O'Rourke, Tom
2015-10-01 8:21 ` Daniel Vetter
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