* [PATCH 01/12] drm/i915: Prepare for multiple workaround lists
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 02/12] drm/i915: Raise the amount of workarounds one list has Mika Kuoppala
` (10 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
In preparation to have separate workaround lists
for both LRI and MMIO written workarounds, parametrize the
register addition and printing of wa lists.
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 39 +++++++++++++++++++++------------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++--------
4 files changed, 37 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3f2a7a7..af44808 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3094,33 +3094,44 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
return 0;
}
-static int i915_wa_registers(struct seq_file *m, void *unused)
+static void print_wa_regs(struct seq_file *m,
+ const struct i915_workarounds *w)
{
- int i;
- int ret;
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ int i;
- ret = mutex_lock_interruptible(&dev->struct_mutex);
- if (ret)
- return ret;
-
- intel_runtime_pm_get(dev_priv);
-
- seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
- for (i = 0; i < dev_priv->workarounds.count; ++i) {
+ for (i = 0; i < w->count; ++i) {
u32 addr, mask, value, read;
bool ok;
- addr = dev_priv->workarounds.reg[i].addr;
- mask = dev_priv->workarounds.reg[i].mask;
- value = dev_priv->workarounds.reg[i].value;
+ addr = w->reg[i].addr;
+ mask = w->reg[i].mask;
+ value = w->reg[i].value;
read = I915_READ(addr);
ok = (value & mask) == (read & mask);
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
addr, value, mask, read, ok ? "OK" : "FAIL");
}
+}
+
+static int i915_wa_registers(struct seq_file *m, void *unused)
+{
+ int ret;
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ ret = mutex_lock_interruptible(&dev->struct_mutex);
+ if (ret)
+ return ret;
+
+ intel_runtime_pm_get(dev_priv);
+
+ seq_printf(m, "Workarounds applied: %d\n",
+ dev_priv->lri_workarounds.count);
+ print_wa_regs(m, &dev_priv->lri_workarounds);
intel_runtime_pm_put(dev_priv);
mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51eea29..aa38d1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1844,7 +1844,7 @@ struct drm_i915_private {
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
- struct i915_workarounds workarounds;
+ struct i915_workarounds lri_workarounds;
/* Reclocking support */
bool render_reclock_avail;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 825fa7a..b9c7d23 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1095,7 +1095,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
struct intel_ringbuffer *ringbuf = req->ringbuf;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct i915_workarounds *w = &dev_priv->workarounds;
+ struct i915_workarounds *w = &dev_priv->lri_workarounds;
if (WARN_ON_ONCE(w->count == 0))
return 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c82c74c..71b4fac 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -715,7 +715,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
struct intel_engine_cs *ring = req->ring;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct i915_workarounds *w = &dev_priv->workarounds;
+ struct i915_workarounds *w = &dev_priv->lri_workarounds;
if (WARN_ON_ONCE(w->count == 0))
return 0;
@@ -763,25 +763,26 @@ static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
return ret;
}
-static int wa_add(struct drm_i915_private *dev_priv,
+static int wa_add(struct i915_workarounds *w,
const u32 addr, const u32 mask, const u32 val)
{
- const u32 idx = dev_priv->workarounds.count;
+ const u32 idx = w->count;
if (WARN_ON(idx >= I915_MAX_WA_REGS))
return -ENOSPC;
- dev_priv->workarounds.reg[idx].addr = addr;
- dev_priv->workarounds.reg[idx].value = val;
- dev_priv->workarounds.reg[idx].mask = mask;
+ w->reg[idx].addr = addr;
+ w->reg[idx].value = val;
+ w->reg[idx].mask = mask;
- dev_priv->workarounds.count++;
+ w->count++;
return 0;
}
#define WA_REG(addr, mask, val) do { \
- const int r = wa_add(dev_priv, (addr), (mask), (val)); \
+ const int r = wa_add(&dev_priv->lri_workarounds, \
+ (addr), (mask), (val)); \
if (r) \
return r; \
} while (0)
@@ -1093,7 +1094,7 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
WARN_ON(ring->id != RCS);
- dev_priv->workarounds.count = 0;
+ dev_priv->lri_workarounds.count = 0;
if (IS_BROADWELL(dev))
return bdw_init_workarounds(ring);
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 02/12] drm/i915: Raise the amount of workarounds one list has
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
2015-10-06 14:26 ` [PATCH 01/12] drm/i915: Prepare for multiple workaround lists Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 03/12] drm/i915: Don't return inside WA_REG macro Mika Kuoppala
` (9 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
As we move towards of adding mmio register setup to
use workaround list, raise the maximum amount of available
registers in list.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index aa38d1e..1883847 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1669,7 +1669,7 @@ struct i915_wa_reg {
u32 mask;
};
-#define I915_MAX_WA_REGS 16
+#define I915_MAX_WA_REGS 32
struct i915_workarounds {
struct i915_wa_reg reg[I915_MAX_WA_REGS];
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 03/12] drm/i915: Don't return inside WA_REG macro
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
2015-10-06 14:26 ` [PATCH 01/12] drm/i915: Prepare for multiple workaround lists Mika Kuoppala
2015-10-06 14:26 ` [PATCH 02/12] drm/i915: Raise the amount of workarounds one list has Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 04/12] drm/i915: Move workaround macros to i915_drv.h Mika Kuoppala
` (8 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
It is considered a very bad practice to return inside
a macro. Instead of returning, emit a warning.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 71b4fac..bc8a8e2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -783,8 +783,7 @@ static int wa_add(struct i915_workarounds *w,
#define WA_REG(addr, mask, val) do { \
const int r = wa_add(&dev_priv->lri_workarounds, \
(addr), (mask), (val)); \
- if (r) \
- return r; \
+ WARN_ON(r); \
} while (0)
#define WA_SET_BIT_MASKED(addr, mask) \
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 04/12] drm/i915: Move workaround macros to i915_drv.h
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (2 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 03/12] drm/i915: Don't return inside WA_REG macro Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 05/12] drm/i915: Specify the wa list in WA_* macros Mika Kuoppala
` (7 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
The plan is to allow workaround list usage outside of
intel_ringbuffer.c, mainly in intel_pm.c where we setup assortment
of workaround registers as part of intel_init_clock_gating().
Move macros to i915_drv.h and export intel_wa_add().
Remove WA_WRITE macro as there are no users of it as of now.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 22 ++++++++++++++++++++++
drivers/gpu/drm/i915/intel_ringbuffer.c | 24 ++----------------------
2 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1883847..5a04948 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3518,4 +3518,26 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
i915_gem_request_assign(&ring->trace_irq_req, req);
}
+/* Workaround register lists */
+#define WA_REG(addr, mask, val) do { \
+ const int r = intel_wa_add(&dev_priv->lri_workarounds, \
+ (addr), (mask), (val)); \
+ WARN_ON(r); \
+ } while (0)
+
+#define WA_SET_BIT_MASKED(addr, mask) \
+ WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
+
+#define WA_CLR_BIT_MASKED(addr, mask) \
+ WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
+
+#define WA_SET_FIELD_MASKED(addr, mask, value) \
+ WA_REG(addr, mask, _MASKED_FIELD(mask, value))
+
+#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ((addr)) | (mask))
+#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ((addr)) & ~(mask))
+
+int intel_wa_add(struct i915_workarounds *w,
+ const u32 addr, const u32 mask, const u32 val);
+
#endif
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index bc8a8e2..29ae97e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -763,8 +763,8 @@ static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
return ret;
}
-static int wa_add(struct i915_workarounds *w,
- const u32 addr, const u32 mask, const u32 val)
+int intel_wa_add(struct i915_workarounds *w,
+ const u32 addr, const u32 mask, const u32 val)
{
const u32 idx = w->count;
@@ -780,26 +780,6 @@ static int wa_add(struct i915_workarounds *w,
return 0;
}
-#define WA_REG(addr, mask, val) do { \
- const int r = wa_add(&dev_priv->lri_workarounds, \
- (addr), (mask), (val)); \
- WARN_ON(r); \
- } while (0)
-
-#define WA_SET_BIT_MASKED(addr, mask) \
- WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
-
-#define WA_CLR_BIT_MASKED(addr, mask) \
- WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
-
-#define WA_SET_FIELD_MASKED(addr, mask, value) \
- WA_REG(addr, mask, _MASKED_FIELD(mask, value))
-
-#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
-#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
-
-#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
-
static int gen8_init_workarounds(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 05/12] drm/i915: Specify the wa list in WA_* macros
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (3 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 04/12] drm/i915: Move workaround macros to i915_drv.h Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 06/12] drm/i915: Introduce mmio workaround list Mika Kuoppala
` (6 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
In order to prepare for different types of workaround lists,
parametrize the list we are adding the workaround register.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 20 +++++-----
drivers/gpu/drm/i915/intel_ringbuffer.c | 65 +++++++++++++++++----------------
2 files changed, 44 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a04948..0ed790c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3519,23 +3519,25 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
}
/* Workaround register lists */
-#define WA_REG(addr, mask, val) do { \
+#define WA_REG_LRI(addr, mask, val) do { \
const int r = intel_wa_add(&dev_priv->lri_workarounds, \
(addr), (mask), (val)); \
WARN_ON(r); \
} while (0)
-#define WA_SET_BIT_MASKED(addr, mask) \
- WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
+#define WA_SET_BIT_MASKED(t, addr, mask) \
+ WA_REG_##t(addr, (mask), _MASKED_BIT_ENABLE(mask))
-#define WA_CLR_BIT_MASKED(addr, mask) \
- WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
+#define WA_CLR_BIT_MASKED(t, addr, mask) \
+ WA_REG_##t(addr, (mask), _MASKED_BIT_DISABLE(mask))
-#define WA_SET_FIELD_MASKED(addr, mask, value) \
- WA_REG(addr, mask, _MASKED_FIELD(mask, value))
+#define WA_SET_FIELD_MASKED(t, addr, mask, value) \
+ WA_REG_##t(addr, mask, _MASKED_FIELD(mask, value))
-#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ((addr)) | (mask))
-#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ((addr)) & ~(mask))
+#define WA_SET_BIT(t, addr, mask) \
+ WA_REG_##t(addr, mask, I915_READ((addr)) | (mask))
+#define WA_CLR_BIT(t, addr, mask) \
+ WA_REG_##t(addr, mask, I915_READ((addr)) & ~(mask))
int intel_wa_add(struct i915_workarounds *w,
const u32 addr, const u32 mask, const u32 val);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 29ae97e..c9d3489e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -785,13 +785,13 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
+ WA_SET_BIT_MASKED(LRI, INSTPM, INSTPM_FORCE_ORDERING);
/* WaDisableAsyncFlipPerfMode:bdw,chv */
- WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+ WA_SET_BIT_MASKED(LRI, MI_MODE, ASYNC_FLIP_PERF_DISABLE);
/* WaDisablePartialInstShootdown:bdw,chv */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+ WA_SET_BIT_MASKED(LRI, GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
/* Use Force Non-Coherent whenever executing a 3D context. This is a
@@ -800,7 +800,7 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
*/
/* WaForceEnableNonCoherent:bdw,chv */
/* WaHdcDisableFetchWhenMasked:bdw,chv */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ WA_SET_BIT_MASKED(LRI, HDC_CHICKEN0,
HDC_DONOT_FETCH_MEM_WHEN_MASKED |
HDC_FORCE_NON_COHERENT);
@@ -812,10 +812,10 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
*
* This optimization is off by default for BDW and CHV; turn it on.
*/
- WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
+ WA_CLR_BIT_MASKED(LRI, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
/* Wa4x4STCOptimizationDisable:bdw,chv */
- WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
+ WA_SET_BIT_MASKED(LRI, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
/*
* BSpec recommends 8x4 when MSAA is used,
@@ -825,7 +825,7 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
* disable bit, which we don't touch here, but it's good
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
*/
- WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+ WA_SET_FIELD_MASKED(LRI, GEN7_GT_MODE,
GEN6_WIZ_HASHING_MASK,
GEN6_WIZ_HASHING_16x4);
@@ -843,16 +843,16 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
return ret;
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+ WA_SET_BIT_MASKED(LRI, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* WaDisableDopClockGating:bdw */
- WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ WA_SET_BIT_MASKED(LRI, GEN7_ROW_CHICKEN2,
DOP_CLOCK_GATING_DISABLE);
- WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
+ WA_SET_BIT_MASKED(LRI, HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ WA_SET_BIT_MASKED(LRI, HDC_CHICKEN0,
/* WaForceContextSaveRestoreNonCoherent:bdw */
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
@@ -872,10 +872,10 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
return ret;
/* WaDisableThreadStallDopClockGating:chv */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+ WA_SET_BIT_MASKED(LRI, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* Improve HiZ throughput on CHV. */
- WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
+ WA_SET_BIT_MASKED(LRI, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
return 0;
}
@@ -887,25 +887,25 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
uint32_t tmp;
/* WaDisablePartialInstShootdown:skl,bxt */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+ WA_SET_BIT_MASKED(LRI, GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
/* Syncing dependencies between camera and graphics:skl,bxt */
- WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
+ WA_SET_BIT_MASKED(LRI, HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
INTEL_REVID(dev) == SKL_REVID_B0)) ||
(IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
- WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
+ WA_CLR_BIT_MASKED(LRI, GEN9_HALF_SLICE_CHICKEN5,
GEN9_DG_MIRROR_FIX_ENABLE);
}
if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
(IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
+ WA_SET_BIT_MASKED(LRI, GEN7_COMMON_SLICE_CHICKEN1,
GEN9_RHWO_OPTIMIZATION_DISABLE);
/*
* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
@@ -917,23 +917,24 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
IS_BROXTON(dev)) {
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
- WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
+ WA_SET_BIT_MASKED(LRI, GEN9_HALF_SLICE_CHICKEN7,
GEN9_ENABLE_YV12_BUGFIX);
}
/* Wa4x4STCOptimizationDisable:skl,bxt */
/* WaDisablePartialResolveInVc:skl,bxt */
- WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
- GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
+ WA_SET_BIT_MASKED(LRI, CACHE_MODE_1,
+ (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
+ GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
/* WaCcsTlbPrefetchDisable:skl,bxt */
- WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
+ WA_CLR_BIT_MASKED(LRI, GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);
/* WaDisableMaskBasedCammingInRCC:skl,bxt */
if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
(IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
- WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
+ WA_SET_BIT_MASKED(LRI, SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
@@ -941,17 +942,17 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
(IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
- WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+ WA_SET_BIT_MASKED(LRI, HDC_CHICKEN0, tmp);
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
if (IS_SKYLAKE(dev) ||
(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
- WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
+ WA_SET_BIT_MASKED(LRI, HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
}
/* WaDisableSTUnitPowerOptimization:skl,bxt */
- WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
+ WA_SET_BIT_MASKED(LRI, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
return 0;
}
@@ -987,7 +988,7 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
return 0;
/* Tune IZ hashing. See intel_device_info_runtime_init() */
- WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+ WA_SET_FIELD_MASKED(LRI, GEN7_GT_MODE,
GEN9_IZ_HASHING_MASK(2) |
GEN9_IZ_HASHING_MASK(1) |
GEN9_IZ_HASHING_MASK(0),
@@ -1011,7 +1012,7 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
/* WaDisablePowerCompilerClockGating:skl */
if (INTEL_REVID(dev) == SKL_REVID_B0)
- WA_SET_BIT_MASKED(HIZ_CHICKEN,
+ WA_SET_BIT_MASKED(LRI, HIZ_CHICKEN,
BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
if (INTEL_REVID(dev) <= SKL_REVID_D0) {
@@ -1021,20 +1022,20 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
* a TLB invalidation occurs during a PSD flush.
*/
/* WaForceEnableNonCoherent:skl */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ WA_SET_BIT_MASKED(LRI, HDC_CHICKEN0,
HDC_FORCE_NON_COHERENT);
}
if (INTEL_REVID(dev) == SKL_REVID_C0 ||
INTEL_REVID(dev) == SKL_REVID_D0)
/* WaBarrierPerformanceFixDisable:skl */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ WA_SET_BIT_MASKED(LRI, HDC_CHICKEN0,
HDC_FENCE_DEST_SLM_DISABLE |
HDC_BARRIER_PERFORMANCE_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:skl */
if (INTEL_REVID(dev) <= SKL_REVID_F0) {
- WA_SET_BIT_MASKED(
+ WA_SET_BIT_MASKED(LRI,
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
@@ -1053,12 +1054,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
return ret;
/* WaDisableThreadStallDopClockGating:bxt */
- WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+ WA_SET_BIT_MASKED(LRI, GEN8_ROW_CHICKEN,
STALL_DOP_GATING_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:bxt */
if (INTEL_REVID(dev) <= BXT_REVID_B0) {
- WA_SET_BIT_MASKED(
+ WA_SET_BIT_MASKED(LRI,
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
--
2.1.4
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 06/12] drm/i915: Introduce mmio workaround list
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (4 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 05/12] drm/i915: Specify the wa list in WA_* macros Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset Mika Kuoppala
` (5 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
Introduce another workaround list for mmio write type of
workarounds. No users yet.
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++++----
2 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index af44808..0c4e6bc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3095,7 +3095,8 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
}
static void print_wa_regs(struct seq_file *m,
- const struct i915_workarounds *w)
+ const struct i915_workarounds *w,
+ const char *type)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
@@ -3111,8 +3112,8 @@ static void print_wa_regs(struct seq_file *m,
value = w->reg[i].value;
read = I915_READ(addr);
ok = (value & mask) == (read & mask);
- seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
- addr, value, mask, read, ok ? "OK" : "FAIL");
+ seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, type: %s, status: %s\n",
+ addr, value, mask, read, type, ok ? "OK" : "FAIL");
}
}
@@ -3130,8 +3131,11 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
intel_runtime_pm_get(dev_priv);
seq_printf(m, "Workarounds applied: %d\n",
- dev_priv->lri_workarounds.count);
- print_wa_regs(m, &dev_priv->lri_workarounds);
+ dev_priv->lri_workarounds.count +
+ dev_priv->mmio_workarounds.count);
+
+ print_wa_regs(m, &dev_priv->lri_workarounds, " LRI");
+ print_wa_regs(m, &dev_priv->mmio_workarounds, "MMIO");
intel_runtime_pm_put(dev_priv);
mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ed790c..ae5b6b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1845,6 +1845,7 @@ struct drm_i915_private {
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
struct i915_workarounds lri_workarounds;
+ struct i915_workarounds mmio_workarounds;
/* Reclocking support */
bool render_reclock_avail;
@@ -3519,12 +3520,17 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
}
/* Workaround register lists */
-#define WA_REG_LRI(addr, mask, val) do { \
- const int r = intel_wa_add(&dev_priv->lri_workarounds, \
- (addr), (mask), (val)); \
- WARN_ON(r); \
+#define WA_REG(wlist, addr, mask, val) do { \
+ const int r = intel_wa_add((wlist), (addr), (mask), (val)); \
+ WARN_ON(r); \
} while (0)
+#define WA_REG_LRI(addr, mask, val) \
+ WA_REG(&dev_priv->lri_workarounds, (addr), (mask), (val))
+
+#define WA_REG_MMIO(addr, mask, val) \
+ WA_REG(&dev_priv->mmio_workarounds, (addr), (mask), (val))
+
#define WA_SET_BIT_MASKED(t, addr, mask) \
WA_REG_##t(addr, (mask), _MASKED_BIT_ENABLE(mask))
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (5 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 06/12] drm/i915: Introduce mmio workaround list Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-07 8:43 ` Chris Wilson
2015-10-07 14:22 ` Daniel Vetter
2015-10-06 14:26 ` [PATCH 08/12] drm/i915: Use mmio workaround list for skl/bxt Mika Kuoppala
` (4 subsequent siblings)
11 siblings, 2 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku, Mika Kuoppala
From: Mika Kuoppala <miku@testikku.fi.intel.com>
Rewrite everything in mmio workaround list right after
gpu reset. This ensures that we start the reinitialization
with proper mmio workarounds in place, before we
start the rings.
This commit just adds the mechanism, the list itself
is still empty. Following commits will add registers.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++
drivers/gpu/drm/i915/i915_irq.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++++++++
5 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ae5b6b3..d41808a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2732,6 +2732,7 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
enum forcewake_domains domains);
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
+void assert_forcewakes_active(struct drm_i915_private *dev_priv);
static inline bool intel_vgpu_active(struct drm_device *dev)
{
return to_i915(dev)->vgpu.active;
@@ -3545,7 +3546,14 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
#define WA_CLR_BIT(t, addr, mask) \
WA_REG_##t(addr, mask, I915_READ((addr)) & ~(mask))
+static inline void intel_wa_init(struct i915_workarounds *w)
+{
+ w->count = 0;
+}
+
int intel_wa_add(struct i915_workarounds *w,
const u32 addr, const u32 mask, const u32 val);
+void intel_wa_write_mmio(struct drm_i915_private *dev_priv,
+ const struct i915_workarounds *w);
#endif
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8ca772d..e686f78 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2441,6 +2441,8 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
*/
ret = i915_reset(dev);
+ intel_wa_write_mmio(dev_priv, &dev_priv->mmio_workarounds);
+
intel_finish_reset(dev);
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 60d120c..e97f271 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -52,6 +52,22 @@
#define INTEL_RC6p_ENABLE (1<<1)
#define INTEL_RC6pp_ENABLE (1<<2)
+void intel_wa_write_mmio(struct drm_i915_private *dev_priv,
+ const struct i915_workarounds *w)
+{
+ int i;
+
+ if (WARN_ON_ONCE(w->count == 0))
+ return;
+
+ assert_forcewakes_active(dev_priv);
+
+ for (i = 0; i < w->count; i++)
+ I915_WRITE_FW(w->reg[i].addr, w->reg[i].value);
+
+ DRM_DEBUG_DRIVER("Number of Workarounds written: %d\n", w->count);
+}
+
static void gen9_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ intel_wa_init(&dev_priv->mmio_workarounds);
+
if (dev_priv->display.init_clock_gating)
dev_priv->display.init_clock_gating(dev);
+
+ intel_wa_write_mmio(dev_priv, &dev_priv->mmio_workarounds);
}
void intel_suspend_hw(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c9d3489e..3667dd9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1074,7 +1074,7 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
WARN_ON(ring->id != RCS);
- dev_priv->lri_workarounds.count = 0;
+ intel_wa_init(&dev_priv->lri_workarounds);
if (IS_BROADWELL(dev))
return bdw_init_workarounds(ring);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index b43c6d0..3f8d1f6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -524,6 +524,18 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
WARN_ON(domain->wake_count);
}
+void assert_forcewakes_active(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore_forcewake_domain *domain;
+ enum forcewake_domain_id id;
+
+ if (!dev_priv->uncore.funcs.force_wake_get)
+ return;
+
+ for_each_fw_domain(domain, dev_priv, id)
+ WARN_ON(domain->wake_count == 0);
+}
+
/* We give fast paths for the really cool registers */
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
((reg) < 0x40000 && (reg) != FORCEWAKE)
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset
2015-10-06 14:26 ` [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset Mika Kuoppala
@ 2015-10-07 8:43 ` Chris Wilson
2015-10-07 13:52 ` Ville Syrjälä
2015-10-07 14:22 ` Daniel Vetter
1 sibling, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2015-10-07 8:43 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx, miku, Mika Kuoppala
On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote:
> @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + intel_wa_init(&dev_priv->mmio_workarounds);
> +
> if (dev_priv->display.init_clock_gating)
> dev_priv->display.init_clock_gating(dev);
> +
> + intel_wa_write_mmio(dev_priv, &dev_priv->mmio_workarounds);
> }
Given that we have this function which is in charge of setting the w/a
regs and is supposed to be called when initialising the hw after
load/reset/resume, why?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset
2015-10-07 8:43 ` Chris Wilson
@ 2015-10-07 13:52 ` Ville Syrjälä
2015-10-07 14:23 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjälä @ 2015-10-07 13:52 UTC (permalink / raw)
To: Chris Wilson, Mika Kuoppala, intel-gfx, miku, Mika Kuoppala
On Wed, Oct 07, 2015 at 09:43:07AM +0100, Chris Wilson wrote:
> On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote:
> > @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> >
> > + intel_wa_init(&dev_priv->mmio_workarounds);
> > +
> > if (dev_priv->display.init_clock_gating)
> > dev_priv->display.init_clock_gating(dev);
> > +
> > + intel_wa_write_mmio(dev_priv, &dev_priv->mmio_workarounds);
> > }
>
> Given that we have this function which is in charge of setting the w/a
> regs and is supposed to be called when initialising the hw after
> load/reset/resume, why?
I think ideally we should move all the GT related w/as, or at least the
ones clobbered by a GPU reset into ring init, or somewhere close by.
The display stuff (and UCGCTL at least) could stay where they are.
Although I suspect we should move the init_clock_gating earlier in the
init/resume sequence anyway. I think now we might be a bit late in doing
it.
--
Ville Syrjälä
Intel OTC
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset
2015-10-07 13:52 ` Ville Syrjälä
@ 2015-10-07 14:23 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2015-10-07 14:23 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, miku, Mika Kuoppala
On Wed, Oct 07, 2015 at 04:52:54PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 07, 2015 at 09:43:07AM +0100, Chris Wilson wrote:
> > On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote:
> > > @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> > > {
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > >
> > > + intel_wa_init(&dev_priv->mmio_workarounds);
> > > +
> > > if (dev_priv->display.init_clock_gating)
> > > dev_priv->display.init_clock_gating(dev);
> > > +
> > > + intel_wa_write_mmio(dev_priv, &dev_priv->mmio_workarounds);
> > > }
> >
> > Given that we have this function which is in charge of setting the w/a
> > regs and is supposed to be called when initialising the hw after
> > load/reset/resume, why?
>
> I think ideally we should move all the GT related w/as, or at least the
> ones clobbered by a GPU reset into ring init, or somewhere close by.
> The display stuff (and UCGCTL at least) could stay where they are.
> Although I suspect we should move the init_clock_gating earlier in the
> init/resume sequence anyway. I think now we might be a bit late in doing
> it.
Yes, this is how it's supposed to work. Any w/a which gets clobbered by GT
reset and which is still in the init_clock_gating code is just plain a bug
in our driver. We have them aplenty unfortunately :(
Maybe we should add a big kerneldoc to intel_init_clock_gating explaining
that.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset
2015-10-06 14:26 ` [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset Mika Kuoppala
2015-10-07 8:43 ` Chris Wilson
@ 2015-10-07 14:22 ` Daniel Vetter
1 sibling, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2015-10-07 14:22 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx, miku, Mika Kuoppala
On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote:
> From: Mika Kuoppala <miku@testikku.fi.intel.com>
>
> Rewrite everything in mmio workaround list right after
> gpu reset. This ensures that we start the reinitialization
> with proper mmio workarounds in place, before we
> start the rings.
>
> This commit just adds the mechanism, the list itself
> is still empty. Following commits will add registers.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++
> drivers/gpu/drm/i915/i915_irq.c | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++++++++
> 5 files changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ae5b6b3..d41808a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2732,6 +2732,7 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
> void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
> enum forcewake_domains domains);
> void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
> +void assert_forcewakes_active(struct drm_i915_private *dev_priv);
> static inline bool intel_vgpu_active(struct drm_device *dev)
> {
> return to_i915(dev)->vgpu.active;
> @@ -3545,7 +3546,14 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
> #define WA_CLR_BIT(t, addr, mask) \
> WA_REG_##t(addr, mask, I915_READ((addr)) & ~(mask))
>
> +static inline void intel_wa_init(struct i915_workarounds *w)
> +{
> + w->count = 0;
> +}
> +
> int intel_wa_add(struct i915_workarounds *w,
> const u32 addr, const u32 mask, const u32 val);
>
> +void intel_wa_write_mmio(struct drm_i915_private *dev_priv,
> + const struct i915_workarounds *w);
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 8ca772d..e686f78 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2441,6 +2441,8 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> */
> ret = i915_reset(dev);
>
> + intel_wa_write_mmio(dev_priv, &dev_priv->mmio_workarounds);
> +
> intel_finish_reset(dev);
>
> intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 60d120c..e97f271 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -52,6 +52,22 @@
> #define INTEL_RC6p_ENABLE (1<<1)
> #define INTEL_RC6pp_ENABLE (1<<2)
>
> +void intel_wa_write_mmio(struct drm_i915_private *dev_priv,
> + const struct i915_workarounds *w)
> +{
> + int i;
> +
> + if (WARN_ON_ONCE(w->count == 0))
> + return;
> +
> + assert_forcewakes_active(dev_priv);
> +
> + for (i = 0; i < w->count; i++)
> + I915_WRITE_FW(w->reg[i].addr, w->reg[i].value);
> +
> + DRM_DEBUG_DRIVER("Number of Workarounds written: %d\n", w->count);
> +}
> +
> static void gen9_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + intel_wa_init(&dev_priv->mmio_workarounds);
> +
> if (dev_priv->display.init_clock_gating)
> dev_priv->display.init_clock_gating(dev);
> +
> + intel_wa_write_mmio(dev_priv, &dev_priv->mmio_workarounds);
init_clock_gating is for display block workarounds, not for anything in
the GT. That should be done by either the various engine/ring init hooks
or by new code. The reason for that is that display and GT can be reset
separately (well GT can be reset without display going down, at least on
modern hw).
-Daniel
> }
>
> void intel_suspend_hw(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c9d3489e..3667dd9 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1074,7 +1074,7 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
>
> WARN_ON(ring->id != RCS);
>
> - dev_priv->lri_workarounds.count = 0;
> + intel_wa_init(&dev_priv->lri_workarounds);
>
> if (IS_BROADWELL(dev))
> return bdw_init_workarounds(ring);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index b43c6d0..3f8d1f6 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -524,6 +524,18 @@ void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
> WARN_ON(domain->wake_count);
> }
>
> +void assert_forcewakes_active(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore_forcewake_domain *domain;
> + enum forcewake_domain_id id;
> +
> + if (!dev_priv->uncore.funcs.force_wake_get)
> + return;
> +
> + for_each_fw_domain(domain, dev_priv, id)
> + WARN_ON(domain->wake_count == 0);
> +}
> +
> /* We give fast paths for the really cool registers */
> #define NEEDS_FORCE_WAKE(dev_priv, reg) \
> ((reg) < 0x40000 && (reg) != FORCEWAKE)
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 08/12] drm/i915: Use mmio workaround list for skl/bxt
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (6 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 09/12] drm/i915/bdw: Use mmio workarounds in init clock gating Mika Kuoppala
` (3 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
Some registers are, naturally, lost in gpu reset/suspend cycle.
And some registers, for example in display domain and are not subject
to gpu reset so they retain their contents.
As hang recovery triggers a reset, recoverable gpu hang can currently
flush out essential workarounds and cause havoc later on.
When register GEN8_GARBNTL is missing the WaEnableGapsTsvCreditFix:skl,
it can cause random system hangs [1]. This workaround was added in:
commit 245d96670d26 ("drm/i915:skl: Add WaEnableGapsTsvCreditFix").
But another set of system hangs were observed and the failure pattern
indicated that there was random gpu hang preceding the system hang [2].
This lead to the realization that we lose this workaround and BDW_SCRATCH1
on reset.
Add workarounds in skl/bxt init clock gating path to mmio workaround
list. This exposes these registers to the same testing mechanism in use
with the lri workarounds, gem_workarounds.
References: [1] https://bugs.freedesktop.org/show_bug.cgi?id=90854
References: https://bugs.freedesktop.org/show_bug.cgi?id=92315
Testcase: igt/gem_workarounds
Reported-by: Tomi Sarvela <tomix.p.sarvela@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 31 +++++++++++++------------------
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e97f271..61136e1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -73,12 +73,11 @@ static void gen9_init_clock_gating(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
/* WaEnableLbsSlaRetryTimerDecrement:skl */
- I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
+ WA_SET_BIT(MMIO, BDW_SCRATCH1,
GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
/* WaDisableKillLogic:bxt,skl */
- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
- ECOCHK_DIS_TLB);
+ WA_SET_BIT(MMIO, GAM_ECOCHK, ECOCHK_DIS_TLB);
}
static void skl_init_clock_gating(struct drm_device *dev)
@@ -89,12 +88,11 @@ static void skl_init_clock_gating(struct drm_device *dev)
if (INTEL_REVID(dev) <= SKL_REVID_D0) {
/* WaDisableHDCInvalidation:skl */
- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
- BDW_DISABLE_HDC_INVALIDATION);
+ WA_SET_BIT(MMIO, GAM_ECOCHK, BDW_DISABLE_HDC_INVALIDATION);
/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
- I915_WRITE(FF_SLICE_CS_CHICKEN2,
- _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
+ WA_SET_BIT_MASKED(MMIO, FF_SLICE_CS_CHICKEN2,
+ GEN9_TSG_BARRIER_ACK_DISABLE);
}
/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
@@ -102,13 +100,12 @@ static void skl_init_clock_gating(struct drm_device *dev)
*/
if (INTEL_REVID(dev) <= SKL_REVID_E0)
/* WaDisableLSQCROPERFforOCL:skl */
- I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
- GEN8_LQSC_RO_PERF_DIS);
+ WA_SET_BIT(MMIO, GEN8_L3SQCREG4, GEN8_LQSC_RO_PERF_DIS);
/* WaEnableGapsTsvCreditFix:skl */
if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
- I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
- GEN9_GAPS_TSV_CREDIT_DISABLE));
+ WA_SET_BIT(MMIO, GEN8_GARBCNTL,
+ GEN9_GAPS_TSV_CREDIT_DISABLE);
}
}
@@ -119,25 +116,23 @@ static void bxt_init_clock_gating(struct drm_device *dev)
gen9_init_clock_gating(dev);
/* WaDisableSDEUnitClockGating:bxt */
- I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
- GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+ WA_SET_BIT(MMIO, GEN8_UCGCTL6, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
/*
* FIXME:
* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
*/
- I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
- GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+ WA_SET_BIT(MMIO, GEN8_UCGCTL6, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
/* WaStoreMultiplePTEenable:bxt */
/* This is a requirement according to Hardware specification */
if (INTEL_REVID(dev) == BXT_REVID_A0)
- I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
+ WA_SET_BIT(MMIO, TILECTL, TILECTL_TLBPF);
/* WaSetClckGatingDisableMedia:bxt */
if (INTEL_REVID(dev) == BXT_REVID_A0) {
- I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
- ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
+ WA_CLR_BIT(MMIO, GEN7_MISCCPCTL,
+ GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE);
}
}
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 09/12] drm/i915/bdw: Use mmio workarounds in init clock gating
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (7 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 08/12] drm/i915: Use mmio workaround list for skl/bxt Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 10/12] drm/i915/hsw: " Mika Kuoppala
` (2 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
For workarounds written in broadwell's init clock gating path,
use mmio workaround list.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 59 ++++++++++++++++++++++++-----------------
2 files changed, 38 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d41808a..a225d55 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3546,6 +3546,9 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
#define WA_CLR_BIT(t, addr, mask) \
WA_REG_##t(addr, mask, I915_READ((addr)) & ~(mask))
+#define WA_WRITE(t, addr, val) \
+ WA_REG_##t(addr, 0xffffffff, val)
+
static inline void intel_wa_init(struct i915_workarounds *w)
{
w->count = 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61136e1..7e01ef7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -62,9 +62,26 @@ void intel_wa_write_mmio(struct drm_i915_private *dev_priv,
assert_forcewakes_active(dev_priv);
- for (i = 0; i < w->count; i++)
+ for (i = 0; i < w->count; i++) {
+ u32 misccpctl;
+
+ /* WaTempDisableDOPClkGating:bdw */
+ const bool need_dop_clkgate =
+ w->reg[i].addr == GEN8_L3SQCREG1 &&
+ IS_BROADWELL(dev_priv->dev);
+
+ if (need_dop_clkgate) {
+ misccpctl = I915_READ(GEN7_MISCCPCTL);
+ I915_WRITE_FW(GEN7_MISCCPCTL,
+ misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ }
+
I915_WRITE_FW(w->reg[i].addr, w->reg[i].value);
+ if (need_dop_clkgate)
+ I915_WRITE_FW(GEN7_MISCCPCTL, misccpctl);
+ }
+
DRM_DEBUG_DRIVER("Number of Workarounds written: %d\n", w->count);
}
@@ -6514,10 +6531,14 @@ static void lpt_init_clock_gating(struct drm_device *dev)
* disabled when not needed anymore in order to save power.
*/
if (HAS_PCH_LPT_LP(dev))
- I915_WRITE(SOUTH_DSPCLK_GATE_D,
- I915_READ(SOUTH_DSPCLK_GATE_D) |
+ WA_SET_BIT(MMIO, SOUTH_DSPCLK_GATE_D,
PCH_LP_PARTITION_LEVEL_DISABLE);
+ /* XXX: This register is volatile with bdw. After
+ * reset you get weird values and after writing,
+ * the value you get is 0x00001000 so read/modify/write
+ * is dangerous
+ */
/* WADPOClockGatingDisable:hsw */
I915_WRITE(TRANS_CHICKEN1(PIPE_A),
I915_READ(TRANS_CHICKEN1(PIPE_A)) |
@@ -6540,52 +6561,42 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe;
- uint32_t misccpctl;
ilk_init_lp_watermarks(dev);
/* WaSwitchSolVfFArbitrationPriority:bdw */
- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+ WA_SET_BIT(MMIO, GAM_ECOCHK, HSW_ECOCHK_ARB_PRIO_SOL);
/* WaPsrDPAMaskVBlankInSRD:bdw */
- I915_WRITE(CHICKEN_PAR1_1,
- I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
+ WA_SET_BIT(MMIO, CHICKEN_PAR1_1, DPA_MASK_VBLANK_SRD);
/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
for_each_pipe(dev_priv, pipe) {
- I915_WRITE(CHICKEN_PIPESL_1(pipe),
- I915_READ(CHICKEN_PIPESL_1(pipe)) |
+ WA_SET_BIT(MMIO, CHICKEN_PIPESL_1(pipe),
BDW_DPRS_MASK_VBLANK_SRD);
}
/* WaVSRefCountFullforceMissDisable:bdw */
/* WaDSRefCountFullforceMissDisable:bdw */
- I915_WRITE(GEN7_FF_THREAD_MODE,
- I915_READ(GEN7_FF_THREAD_MODE) &
- ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
+ WA_CLR_BIT(MMIO, GEN7_FF_THREAD_MODE,
+ GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME);
- I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+ WA_SET_BIT_MASKED(MMIO, GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE);
/* WaDisableSDEUnitClockGating:bdw */
- I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+ WA_SET_BIT(MMIO, GEN8_UCGCTL6,
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
- /*
- * WaProgramL3SqcReg1Default:bdw
- * WaTempDisableDOPClkGating:bdw
- */
- misccpctl = I915_READ(GEN7_MISCCPCTL);
- I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
- I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
- I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+ /* WaProgramL3SqcReg1Default:bdw */
+ WA_WRITE(MMIO, GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
/*
* WaGttCachingOffByDefault:bdw
* GTT cache may not work with big pages, so if those
* are ever enabled GTT cache may need to be disabled.
*/
- I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
+ WA_WRITE(MMIO, HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
lpt_init_clock_gating(dev);
}
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 10/12] drm/i915/hsw: Use mmio workarounds in init clock gating
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (8 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 09/12] drm/i915/bdw: Use mmio workarounds in init clock gating Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 11/12] drm/i915/ivb: " Mika Kuoppala
2015-10-06 14:26 ` [PATCH 12/12] drm/i915/ivb: Simplify row chicken setup logic Mika Kuoppala
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
For workarounds written in haswells's init clock gating path,
use mmio workaround list.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 35 +++++++++++++++--------------------
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e01ef7..b2626c2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6608,29 +6608,26 @@ static void haswell_init_clock_gating(struct drm_device *dev)
ilk_init_lp_watermarks(dev);
/* L3 caching of data atomics doesn't work -- disable it. */
- I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
- I915_WRITE(HSW_ROW_CHICKEN3,
- _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
+ WA_WRITE(MMIO, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
+ WA_SET_BIT_MASKED(MMIO, HSW_ROW_CHICKEN3,
+ HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE);
/* This is required by WaCatErrorRejectionIssue:hsw */
- I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
- I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
- GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+ WA_SET_BIT(MMIO, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+ GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
/* WaVSRefCountFullforceMissDisable:hsw */
- I915_WRITE(GEN7_FF_THREAD_MODE,
- I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
+ WA_CLR_BIT(MMIO, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
/* WaDisable_RenderCache_OperationalFlush:hsw */
- I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
+ WA_CLR_BIT_MASKED(MMIO, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
/* enable HiZ Raw Stall Optimization */
- I915_WRITE(CACHE_MODE_0_GEN7,
- _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+ WA_CLR_BIT_MASKED(MMIO, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
/* WaDisable4x2SubspanOptimization:hsw */
- I915_WRITE(CACHE_MODE_1,
- _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+ WA_SET_BIT_MASKED(MMIO, CACHE_MODE_1,
+ PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
/*
* BSpec recommends 8x4 when MSAA is used,
@@ -6640,19 +6637,17 @@ static void haswell_init_clock_gating(struct drm_device *dev)
* disable bit, which we don't touch here, but it's good
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
*/
- I915_WRITE(GEN7_GT_MODE,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
+ WA_SET_FIELD_MASKED(MMIO, GEN7_GT_MODE,
+ GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4);
/* WaSampleCChickenBitEnable:hsw */
- I915_WRITE(HALF_SLICE_CHICKEN3,
- _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
+ WA_SET_BIT_MASKED(MMIO, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
/* WaSwitchSolVfFArbitrationPriority:hsw */
- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+ WA_SET_BIT(MMIO, GAM_ECOCHK, HSW_ECOCHK_ARB_PRIO_SOL);
/* WaRsPkgCStateDisplayPMReq:hsw */
- I915_WRITE(CHICKEN_PAR1_1,
- I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+ WA_SET_BIT(MMIO, CHICKEN_PAR1_1, FORCE_ARB_IDLE_PLANES);
lpt_init_clock_gating(dev);
}
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 11/12] drm/i915/ivb: Use mmio workarounds in init clock gating
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (9 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 10/12] drm/i915/hsw: " Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
2015-10-06 14:26 ` [PATCH 12/12] drm/i915/ivb: Simplify row chicken setup logic Mika Kuoppala
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
Use workarounds written in ivybridge's init clock gating path,
use mmio workaround list to ensure proper setup after
reset/resume.
This way we don't lose _3DCHICKEN and GEN7_FF_THREAD_MODE register
contents on reset/suspend.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 83 +++++++++++++++++++----------------------
2 files changed, 40 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a7c9e8c..573e7d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5911,7 +5911,7 @@ enum skl_disp_power_wells {
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
+# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1<<10)
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
#define COMMON_SLICE_CHICKEN2 0x7014
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b2626c2..8bc1d3b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6370,11 +6370,11 @@ static void cpt_init_clock_gating(struct drm_device *dev)
* gating for the panel power sequencer or it will fail to
* start up when no ports are active.
*/
- I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
- PCH_DPLUNIT_CLOCK_GATE_DISABLE |
- PCH_CPUNIT_CLOCK_GATE_DISABLE);
- I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
- DPLS_EDP_PPS_FIX_DIS);
+ WA_WRITE(MMIO, SOUTH_DSPCLK_GATE_D,
+ PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
+ PCH_DPLUNIT_CLOCK_GATE_DISABLE |
+ PCH_CPUNIT_CLOCK_GATE_DISABLE);
+ WA_SET_BIT(MMIO, SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS);
/* The below fixes the weird display corruption, a few pixels shifted
* downward, on (only) LVDS of some HP laptops with IVY.
*/
@@ -6387,12 +6387,12 @@ static void cpt_init_clock_gating(struct drm_device *dev)
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
- I915_WRITE(TRANS_CHICKEN2(pipe), val);
+ WA_WRITE(MMIO, TRANS_CHICKEN2(pipe), val);
}
/* WADP0ClockGatingDisable */
for_each_pipe(dev_priv, pipe) {
- I915_WRITE(TRANS_CHICKEN1(pipe),
- TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
+ WA_WRITE(MMIO, TRANS_CHICKEN1(pipe),
+ TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
}
@@ -6519,7 +6519,7 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
reg |= GEN7_FF_VS_SCHED_HW;
reg |= GEN7_FF_DS_SCHED_HW;
- I915_WRITE(GEN7_FF_THREAD_MODE, reg);
+ WA_WRITE(MMIO, GEN7_FF_THREAD_MODE, reg);
}
static void lpt_init_clock_gating(struct drm_device *dev)
@@ -6659,60 +6659,55 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
ilk_init_lp_watermarks(dev);
- I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
+ WA_WRITE(MMIO, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
/* WaDisableEarlyCull:ivb */
- I915_WRITE(_3D_CHICKEN3,
- _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
+ WA_SET_BIT_MASKED(MMIO, _3D_CHICKEN3,
+ _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
/* WaDisableBackToBackFlipFix:ivb */
- I915_WRITE(IVB_CHICKEN3,
- CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
- CHICKEN3_DGMG_DONE_FIX_DISABLE);
+ WA_WRITE(MMIO, IVB_CHICKEN3, CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
+ CHICKEN3_DGMG_DONE_FIX_DISABLE);
/* WaDisablePSDDualDispatchEnable:ivb */
if (IS_IVB_GT1(dev))
- I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
- _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
+ WA_SET_BIT_MASKED(MMIO, GEN7_HALF_SLICE_CHICKEN1,
+ GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
/* WaDisable_RenderCache_OperationalFlush:ivb */
- I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
+ WA_CLR_BIT_MASKED(MMIO, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
- I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
- GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
+ WA_SET_BIT_MASKED(MMIO, GEN7_COMMON_SLICE_CHICKEN1,
+ GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
/* WaApplyL3ControlAndL3ChickenMode:ivb */
- I915_WRITE(GEN7_L3CNTLREG1,
- GEN7_WA_FOR_GEN7_L3_CONTROL);
- I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
- GEN7_WA_L3_CHICKEN_MODE);
+ WA_WRITE(MMIO, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
+ WA_WRITE(MMIO, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
+
if (IS_IVB_GT1(dev))
- I915_WRITE(GEN7_ROW_CHICKEN2,
- _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+ WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2,
+ DOP_CLOCK_GATING_DISABLE);
else {
/* must write both registers */
- I915_WRITE(GEN7_ROW_CHICKEN2,
- _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
- I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
- _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+ WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2,
+ DOP_CLOCK_GATING_DISABLE);
+ WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2_GT2,
+ DOP_CLOCK_GATING_DISABLE);
}
/* WaForceL3Serialization:ivb */
- I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
- ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
+ WA_CLR_BIT(MMIO, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
/*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
* This implements the WaDisableRCZUnitClockGating:ivb workaround.
*/
- I915_WRITE(GEN6_UCGCTL2,
- GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
+ WA_WRITE(MMIO, GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
/* This is required by WaCatErrorRejectionIssue:ivb */
- I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
- I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
- GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+ WA_SET_BIT(MMIO, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+ GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
g4x_disable_trickle_feed(dev);
@@ -6720,13 +6715,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
if (0) { /* causes HiZ corruption on ivb:gt1 */
/* enable HiZ Raw Stall Optimization */
- I915_WRITE(CACHE_MODE_0_GEN7,
- _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+ WA_CLR_BIT_MASKED(MMIO, CACHE_MODE_0_GEN7,
+ HIZ_RAW_STALL_OPT_DISABLE);
}
/* WaDisable4x2SubspanOptimization:ivb */
- I915_WRITE(CACHE_MODE_1,
- _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+ WA_SET_BIT_MASKED(MMIO, CACHE_MODE_1,
+ PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
/*
* BSpec recommends 8x4 when MSAA is used,
@@ -6736,13 +6731,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
* disable bit, which we don't touch here, but it's good
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
*/
- I915_WRITE(GEN7_GT_MODE,
- _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
+ WA_SET_FIELD_MASKED(MMIO, GEN7_GT_MODE,
+ GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4);
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
snpcr &= ~GEN6_MBC_SNPCR_MASK;
snpcr |= GEN6_MBC_SNPCR_MED;
- I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
+ WA_WRITE(MMIO, GEN6_MBCUNIT_SNPCR, snpcr);
if (!HAS_PCH_NOP(dev))
cpt_init_clock_gating(dev);
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 12/12] drm/i915/ivb: Simplify row chicken setup logic
2015-10-06 14:26 [PATCH 00/12] MMIO workaround list Mika Kuoppala
` (10 preceding siblings ...)
2015-10-06 14:26 ` [PATCH 11/12] drm/i915/ivb: " Mika Kuoppala
@ 2015-10-06 14:26 ` Mika Kuoppala
11 siblings, 0 replies; 17+ messages in thread
From: Mika Kuoppala @ 2015-10-06 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: miku
We always write the ROW_CHICKEN2. Make this more clear
by writing it unconditionally.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8bc1d3b..ec77e04 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6685,16 +6685,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
WA_WRITE(MMIO, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
WA_WRITE(MMIO, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
- if (IS_IVB_GT1(dev))
- WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2,
- DOP_CLOCK_GATING_DISABLE);
- else {
- /* must write both registers */
- WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2,
- DOP_CLOCK_GATING_DISABLE);
+ WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2,
+ DOP_CLOCK_GATING_DISABLE);
+
+ /* must write both registers */
+ if (!IS_IVB_GT1(dev))
WA_SET_BIT_MASKED(MMIO, GEN7_ROW_CHICKEN2_GT2,
DOP_CLOCK_GATING_DISABLE);
- }
/* WaForceL3Serialization:ivb */
WA_CLR_BIT(MMIO, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
--
2.1.4
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^ permalink raw reply related [flat|nested] 17+ messages in thread