From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Sarah Sharp <sarah.a.sharp@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it
Date: Tue, 13 Oct 2015 16:17:02 +0300 [thread overview]
Message-ID: <20151013131702.GP26517@intel.com> (raw)
In-Reply-To: <87mvvm52o0.fsf@intel.com>
On Tue, Oct 13, 2015 at 04:16:47PM +0300, Jani Nikula wrote:
> On Wed, 07 Oct 2015, Jani Nikula <jani.nikula@intel.com> wrote:
> > On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >> On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote:
> >>> On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >>> > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote:
> >>> >> Prefer inclusive ranges for revision checks rather than "below B0". Per
> >>> >> specs A2 is not used, so revid <= A1 matches revid < B0.
> >>> >
> >>> > The w/a db would say UNTIL_B0 etc., so might be easier to check against
> >>> > it if we keep to the same convention.
> >>>
> >>> So I wanted to double check what the convention is. I picked
> >>> WaRsDisableCoarsePowerGating.
> >>>
> >>> KBL - SIWA_FOREVER
> >>> BXT - SI_WA_BEFORE(BXT_REV_ID_B0)
> >>> SKL - SIWA_UNTIL_SKL_E0
> >>>
> >>> Description "Disable coarse power gating for GT4 until GT F0 stepping."
> >>>
> >>> *rolls eyes*
> >>>
> >>> So is that "until" there inclusive or non-inclusive? The db is
> >>> contradicting itself...
> >>
> >> Hmm. My recollection was that it's exclusive, but now that I look at
> >> your findings and some other workarounds, it does look a bit more like
> >> inclusive.
> >>
> >> I would think the exclusive thing would be easier to maintain since
> >> the hsd specifies the stepping in which stuff got fixed, and the
> >> exclusive convention would then have the same stepping listed. Eg. if
> >> the hsd says fixed in E0, but the w/a db says UNTIL_D0, then one is
> >> left wondering about D1+ But perhaps such steppings didn't even exist.
> >>
> >> Well, in reality it's all over the place. Eg. looking at the BDW UNTIL_D0
> >> stuff, some are fixed in E0, some are fixed in D0, and at least one was
> >> fixed in B0 according to hsd. So I'm starting to think that the meaning
> >> of the tag depends entirely on the person who pushed the change.
> >
> > With that, I stand by the patches I submitted as they are.
>
> Ville, opinions, r-b, nak, ack, crap, what? ;)
Yeah, I guess it's all good.
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2015-10-13 13:17 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-06 11:41 [PATCH 1/3] drm/i915: remove parens around revision ids Jani Nikula
2015-10-06 11:41 ` [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it Jani Nikula
2015-10-06 12:29 ` Ville Syrjälä
2015-10-06 13:43 ` Jani Nikula
2015-10-06 17:50 ` Vivi, Rodrigo
2015-10-06 19:02 ` Ville Syrjälä
2015-10-07 8:32 ` Jani Nikula
2015-10-13 13:16 ` Jani Nikula
2015-10-13 13:17 ` Ville Syrjälä [this message]
2015-10-06 11:41 ` [PATCH 3/3] drm/i915: add helpers for platform specific revision id range checks Jani Nikula
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