From: Daniel Vetter <daniel@ffwll.ch>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw
Date: Tue, 13 Oct 2015 15:43:21 +0200 [thread overview]
Message-ID: <20151013134321.GA26718@phenom.ffwll.local> (raw)
In-Reply-To: <20151013133501.GX26718@phenom.ffwll.local>
On Tue, Oct 13, 2015 at 03:35:01PM +0200, Daniel Vetter wrote:
> On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote:
> > Op 23-09-15 om 17:34 schreef Gabriel Feceoru:
> > > Using 2 connectors (DVI and VGA) will cause wrpll to be set for
> > > INTEL_OUTPUT_HDMI but never reset if switching to INTEL_OUTPUT_VGA
> > >
> > > Supresses errors like these:
> > > [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.wrpll
> > >
> > Looks like a good idea to always zero it.
>
> Except that we still have a bunch of cases where we recompute clock state
> but only partially. Can we just move them all up into a common place
> please? That would also catch cases where we simply forget to fill this
> out at all.
>
> One case I noticed is edp in skl_ddi_pll_select, but there's probably
> more.
Specifically I think we should move the memset into
intel_modeset_pipe_config and remove it from all the clock compute/pll
select functions. Last time we wanted to do that it wasn't yet possible
because the atomice modeset conversion and shared dpll tracking needed the
old values, but that should be fixed now with crtc_state structures being
completely free-standing.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2015-10-13 13:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-23 15:34 [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw Gabriel Feceoru
2015-10-13 13:18 ` Maarten Lankhorst
2015-10-13 13:35 ` Daniel Vetter
2015-10-13 13:43 ` Daniel Vetter [this message]
2015-10-13 13:43 ` Maarten Lankhorst
2015-10-13 13:58 ` Daniel Vetter
2015-10-13 14:00 ` Maarten Lankhorst
2015-10-13 14:08 ` Daniel Vetter
2015-10-14 8:21 ` Ander Conselvan De Oliveira
2015-10-14 12:44 ` Daniel Vetter
2015-10-14 13:58 ` Ander Conselvan De Oliveira
2015-10-14 15:03 ` Daniel Vetter
2015-11-10 12:53 ` Jani Nikula
2015-11-11 9:25 ` Ander Conselvan De Oliveira
2015-11-11 14:21 ` Jani Nikula
2015-11-11 16:41 ` [PATCH] drm/i915: Clear DDI pll selection in intel_crtc_compute_config() Ander Conselvan de Oliveira
2015-11-11 18:27 ` [PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw Gabriel Feceoru
2015-11-12 8:28 ` Lankhorst, Maarten
2015-11-12 18:35 ` Gabriel Feceoru
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