Re: [PATCH 2/2] drm/i915/skl+: Enable pipe CSC on cursor planes.

Bob Paauwe
2015-08-28T15:56:09Z

On Fri, 28 Aug 2015 15:19:04 +0100
Daniel Stone <daniel@fooishbar.org> wrote:

> Hi Bob,
>
> On 27 August 2015 at 21:46, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> > Extend this to SKL and BXT as it's needed for these platforms as well.
> >
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 88f9764..007bf7d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10001,7 +10001,8 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
> > }
> > cntl |= pipe << 28; /* Connect to correct pipe */
> >
> > - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
> > + IS_SKYLAKE(dev) || IS_BROXTON(dev))
> > cntl |= CURSOR_PIPE_CSC_ENABLE;
>
> For both this and the previous patch, cf. the corresponding patch for
> HSW/BDW[0], have you ensured these values are sanitised at startup,
> even if UEFI hasn't set something clever? Enabling fastboot on my
> (UEFI-based) BDW caused a black screen because were enabling CSC but
> with an empty table.
>
> Cheers,
> Daniel
>
> [0]: https://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg67294.html

Hmm, no I didn't. I assumed that it was all set up correctly since for
SKL+ the primary plane always has PIPE_CSC enabled. My two patches are
just to ensure that both the cursor and sprite planes also have it
enabled. If all the planes are configured the same, it causes a lot of
CRC failures in the igt tests.

Unless I'm missing something (very possible), the pipe CSC setup/lack of
setup is a separate issue.

Looking at Maarten's patch, it looks like mine above should have been
written as

if (HAS_DDI(dev))

instead of all the separate conditions.

Bob

--
--
Bob Paauwe
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193