From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Imre Deak <imre.deak@intel.com>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [Intel-gfx] [PATCH] drm: Explicitly compute the last cacheline for clflush on range
Date: Mon, 19 Oct 2015 10:35:45 +0200 [thread overview]
Message-ID: <20151019083545.GN13786@phenom.ffwll.local> (raw)
In-Reply-To: <20151018160706.GE27143@nuc-i3427.alporthouse.com>
On Sun, Oct 18, 2015 at 05:07:06PM +0100, Chris Wilson wrote:
> On Sun, Oct 18, 2015 at 02:07:13PM +0100, Chris Wilson wrote:
> > > I couldn't spot the difference either. I am beginning to suspect it is
> > > gcc as
> > >
> > > diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> > > index 6743ff7..c9097b5 100644
> > > --- a/drivers/gpu/drm/drm_cache.c
> > > +++ b/drivers/gpu/drm/drm_cache.c
> > > @@ -130,11 +130,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
> > > {
> > > #if defined(CONFIG_X86)
> > > if (cpu_has_clflush) {
> > > const int size = boot_cpu_data.x86_clflush_size;
> > > - void *end = addr + length;
> > > + void *end = addr + length - 1;
> > > addr = (void *)(((unsigned long)addr) & -size);
> > > mb();
> > > - for (; addr < end; addr += size)
> > > + for (; addr <= end; addr += size)
> > > clflushopt(addr);
> > > mb();
> > > return;
> >
> > s/clflushopt/clflush/ works just as well.
> >
> > Plot thickens. Current guess is that gcc doesn't see the constraints
> > underneath the alternative()?
>
> Adding a barrier() after clflushopt() in the loop is sufficient as well.
> Almost certain that alternative() is confusing gcc.
So adding that barrier() to clflushopt with a massive comment that gcc
gets confused?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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prev parent reply other threads:[~2015-10-19 8:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-16 19:55 [PATCH] drm: Explicitly compute the last cacheline for clflush on range Chris Wilson
2015-10-17 20:03 ` Imre Deak
2015-10-18 12:28 ` Chris Wilson
2015-10-18 13:07 ` Chris Wilson
2015-10-18 16:07 ` [Intel-gfx] " Chris Wilson
2015-10-19 8:35 ` Daniel Vetter [this message]
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