* [PATCH 1/6] drm/i195: Rename gt_irq_handler variable
2015-10-20 9:23 [PATCH 0/6] lrc lifecycle cleanups Nick Hoath
@ 2015-10-20 9:23 ` Nick Hoath
2015-10-20 9:23 ` [PATCH 2/6] drm/i915: Break out common code from gen8_gt_irq_handler Nick Hoath
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Nick Hoath @ 2015-10-20 9:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
Renamed tmp variable to the more descriptive iir. (Daniel Vetter/
Thomas Daniel)
Issue: VIZ-4277
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: David Gordon <david.s.gordon@intel.com>
Cc: Thomas Daniel <thomas.daniel@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++++++++++---------------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d68328f..fbf9153 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1296,64 +1296,64 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
irqreturn_t ret = IRQ_NONE;
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
- u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
- if (tmp) {
- I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
+ u32 iir = I915_READ_FW(GEN8_GT_IIR(0));
+ if (iir) {
+ I915_WRITE_FW(GEN8_GT_IIR(0), iir);
ret = IRQ_HANDLED;
- if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
+ if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
intel_lrc_irq_handler(&dev_priv->ring[RCS]);
- if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
+ if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
notify_ring(&dev_priv->ring[RCS]);
- if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
+ if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
intel_lrc_irq_handler(&dev_priv->ring[BCS]);
- if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
+ if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
notify_ring(&dev_priv->ring[BCS]);
} else
DRM_ERROR("The master control interrupt lied (GT0)!\n");
}
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
- u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
- if (tmp) {
- I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
+ u32 iir = I915_READ_FW(GEN8_GT_IIR(1));
+ if (iir) {
+ I915_WRITE_FW(GEN8_GT_IIR(1), iir);
ret = IRQ_HANDLED;
- if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
+ if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
intel_lrc_irq_handler(&dev_priv->ring[VCS]);
- if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
+ if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
notify_ring(&dev_priv->ring[VCS]);
- if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
+ if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
- if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
+ if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
notify_ring(&dev_priv->ring[VCS2]);
} else
DRM_ERROR("The master control interrupt lied (GT1)!\n");
}
if (master_ctl & GEN8_GT_VECS_IRQ) {
- u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
- if (tmp) {
- I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
+ u32 iir = I915_READ_FW(GEN8_GT_IIR(3));
+ if (iir) {
+ I915_WRITE_FW(GEN8_GT_IIR(3), iir);
ret = IRQ_HANDLED;
- if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
+ if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
intel_lrc_irq_handler(&dev_priv->ring[VECS]);
- if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
+ if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
notify_ring(&dev_priv->ring[VECS]);
} else
DRM_ERROR("The master control interrupt lied (GT3)!\n");
}
if (master_ctl & GEN8_GT_PM_IRQ) {
- u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
- if (tmp & dev_priv->pm_rps_events) {
+ u32 iir = I915_READ_FW(GEN8_GT_IIR(2));
+ if (iir & dev_priv->pm_rps_events) {
I915_WRITE_FW(GEN8_GT_IIR(2),
- tmp & dev_priv->pm_rps_events);
+ iir & dev_priv->pm_rps_events);
ret = IRQ_HANDLED;
- gen6_rps_irq_handler(dev_priv, tmp);
+ gen6_rps_irq_handler(dev_priv, iir);
} else
DRM_ERROR("The master control interrupt lied (PM)!\n");
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 2/6] drm/i915: Break out common code from gen8_gt_irq_handler
2015-10-20 9:23 [PATCH 0/6] lrc lifecycle cleanups Nick Hoath
2015-10-20 9:23 ` [PATCH 1/6] drm/i195: Rename gt_irq_handler variable Nick Hoath
@ 2015-10-20 9:23 ` Nick Hoath
2015-10-20 12:12 ` Daniel Vetter
2015-10-20 9:23 ` [PATCH 3/6] drm/i915: Unify execlist and legacy request life-cycles Nick Hoath
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Nick Hoath @ 2015-10-20 9:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
Break out common code from gen8_gt_irq_handler and put it in to
an always inlined function. gcc optimises out the shift at compile
time. (Thomas Daniel/Daniel Vetter/Chris Wilson)
Issue: VIZ-4277
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Cc: Thomas Daniel <thomas.daniel@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_irq.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fbf9153..7837f5e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1290,6 +1290,16 @@ static void snb_gt_irq_handler(struct drm_device *dev,
ivybridge_parity_error_irq_handler(dev, gt_iir);
}
+static __always_inline void
+ gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir,
+ int test_shift)
+{
+ if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
+ notify_ring(ring);
+ if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
+ intel_lrc_irq_handler(ring);
+}
+
static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
u32 master_ctl)
{
@@ -1301,15 +1311,11 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
I915_WRITE_FW(GEN8_GT_IIR(0), iir);
ret = IRQ_HANDLED;
- if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
- intel_lrc_irq_handler(&dev_priv->ring[RCS]);
- if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
- notify_ring(&dev_priv->ring[RCS]);
+ gen8_cs_irq_handler(&dev_priv->ring[RCS],
+ iir, GEN8_RCS_IRQ_SHIFT);
- if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
- intel_lrc_irq_handler(&dev_priv->ring[BCS]);
- if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
- notify_ring(&dev_priv->ring[BCS]);
+ gen8_cs_irq_handler(&dev_priv->ring[BCS],
+ iir, GEN8_BCS_IRQ_SHIFT);
} else
DRM_ERROR("The master control interrupt lied (GT0)!\n");
}
@@ -1320,15 +1326,11 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
I915_WRITE_FW(GEN8_GT_IIR(1), iir);
ret = IRQ_HANDLED;
- if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
- intel_lrc_irq_handler(&dev_priv->ring[VCS]);
- if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
- notify_ring(&dev_priv->ring[VCS]);
+ gen8_cs_irq_handler(&dev_priv->ring[VCS],
+ iir, GEN8_VCS1_IRQ_SHIFT);
- if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
- intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
- if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
- notify_ring(&dev_priv->ring[VCS2]);
+ gen8_cs_irq_handler(&dev_priv->ring[VCS2],
+ iir, GEN8_VCS2_IRQ_SHIFT);
} else
DRM_ERROR("The master control interrupt lied (GT1)!\n");
}
@@ -1339,10 +1341,8 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
I915_WRITE_FW(GEN8_GT_IIR(3), iir);
ret = IRQ_HANDLED;
- if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
- intel_lrc_irq_handler(&dev_priv->ring[VECS]);
- if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
- notify_ring(&dev_priv->ring[VECS]);
+ gen8_cs_irq_handler(&dev_priv->ring[VECS],
+ iir, GEN8_VECS_IRQ_SHIFT);
} else
DRM_ERROR("The master control interrupt lied (GT3)!\n");
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/6] drm/i915: Break out common code from gen8_gt_irq_handler
2015-10-20 9:23 ` [PATCH 2/6] drm/i915: Break out common code from gen8_gt_irq_handler Nick Hoath
@ 2015-10-20 12:12 ` Daniel Vetter
2015-10-20 12:40 ` Chris Wilson
0 siblings, 1 reply; 13+ messages in thread
From: Daniel Vetter @ 2015-10-20 12:12 UTC (permalink / raw)
To: Nick Hoath; +Cc: intel-gfx, Daniel Vetter
On Tue, Oct 20, 2015 at 10:23:52AM +0100, Nick Hoath wrote:
> Break out common code from gen8_gt_irq_handler and put it in to
> an always inlined function. gcc optimises out the shift at compile
> time. (Thomas Daniel/Daniel Vetter/Chris Wilson)
>
> Issue: VIZ-4277
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> Cc: Thomas Daniel <thomas.daniel@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
Merged the first two patches to dinq, thanks.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_irq.c | 40 ++++++++++++++++++++--------------------
> 1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index fbf9153..7837f5e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1290,6 +1290,16 @@ static void snb_gt_irq_handler(struct drm_device *dev,
> ivybridge_parity_error_irq_handler(dev, gt_iir);
> }
>
> +static __always_inline void
> + gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir,
> + int test_shift)
> +{
> + if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
> + notify_ring(ring);
> + if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
> + intel_lrc_irq_handler(ring);
> +}
> +
> static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
> {
> @@ -1301,15 +1311,11 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> I915_WRITE_FW(GEN8_GT_IIR(0), iir);
> ret = IRQ_HANDLED;
>
> - if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
> - intel_lrc_irq_handler(&dev_priv->ring[RCS]);
> - if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
> - notify_ring(&dev_priv->ring[RCS]);
> + gen8_cs_irq_handler(&dev_priv->ring[RCS],
> + iir, GEN8_RCS_IRQ_SHIFT);
>
> - if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
> - intel_lrc_irq_handler(&dev_priv->ring[BCS]);
> - if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
> - notify_ring(&dev_priv->ring[BCS]);
> + gen8_cs_irq_handler(&dev_priv->ring[BCS],
> + iir, GEN8_BCS_IRQ_SHIFT);
> } else
> DRM_ERROR("The master control interrupt lied (GT0)!\n");
> }
> @@ -1320,15 +1326,11 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> I915_WRITE_FW(GEN8_GT_IIR(1), iir);
> ret = IRQ_HANDLED;
>
> - if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
> - intel_lrc_irq_handler(&dev_priv->ring[VCS]);
> - if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
> - notify_ring(&dev_priv->ring[VCS]);
> + gen8_cs_irq_handler(&dev_priv->ring[VCS],
> + iir, GEN8_VCS1_IRQ_SHIFT);
>
> - if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
> - intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
> - if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
> - notify_ring(&dev_priv->ring[VCS2]);
> + gen8_cs_irq_handler(&dev_priv->ring[VCS2],
> + iir, GEN8_VCS2_IRQ_SHIFT);
> } else
> DRM_ERROR("The master control interrupt lied (GT1)!\n");
> }
> @@ -1339,10 +1341,8 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
> I915_WRITE_FW(GEN8_GT_IIR(3), iir);
> ret = IRQ_HANDLED;
>
> - if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
> - intel_lrc_irq_handler(&dev_priv->ring[VECS]);
> - if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
> - notify_ring(&dev_priv->ring[VECS]);
> + gen8_cs_irq_handler(&dev_priv->ring[VECS],
> + iir, GEN8_VECS_IRQ_SHIFT);
> } else
> DRM_ERROR("The master control interrupt lied (GT3)!\n");
> }
> --
> 1.9.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 2/6] drm/i915: Break out common code from gen8_gt_irq_handler
2015-10-20 12:12 ` Daniel Vetter
@ 2015-10-20 12:40 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2015-10-20 12:40 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Daniel Vetter
On Tue, Oct 20, 2015 at 02:12:21PM +0200, Daniel Vetter wrote:
> On Tue, Oct 20, 2015 at 10:23:52AM +0100, Nick Hoath wrote:
> > Break out common code from gen8_gt_irq_handler and put it in to
> > an always inlined function. gcc optimises out the shift at compile
> > time. (Thomas Daniel/Daniel Vetter/Chris Wilson)
> >
> > Issue: VIZ-4277
> > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> > Cc: Thomas Daniel <thomas.daniel@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
>
> Merged the first two patches to dinq, thanks.
> -Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 40 ++++++++++++++++++++--------------------
> > 1 file changed, 20 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index fbf9153..7837f5e 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -1290,6 +1290,16 @@ static void snb_gt_irq_handler(struct drm_device *dev,
> > ivybridge_parity_error_irq_handler(dev, gt_iir);
> > }
> >
> > +static __always_inline void
> > + gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir,
> > + int test_shift)
Pray tell you fixed the formatting first?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/6] drm/i915: Unify execlist and legacy request life-cycles
2015-10-20 9:23 [PATCH 0/6] lrc lifecycle cleanups Nick Hoath
2015-10-20 9:23 ` [PATCH 1/6] drm/i195: Rename gt_irq_handler variable Nick Hoath
2015-10-20 9:23 ` [PATCH 2/6] drm/i915: Break out common code from gen8_gt_irq_handler Nick Hoath
@ 2015-10-20 9:23 ` Nick Hoath
2015-10-20 9:53 ` Chris Wilson
2015-10-20 9:23 ` [PATCH 4/6] drm/i915: Improve dynamic management/eviction of lrc backing objects Nick Hoath
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Nick Hoath @ 2015-10-20 9:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
There is a desire to simplify the i915 driver by reducing the number of
different code paths introduced by the LRC / execlists support. As the
execlists request is now part of the gem request it is possible and
desirable to unify the request life-cycles for execlist and legacy
requests.
A request is considered retireable if its seqno passed (i.e. the request
has completed) and either it was never submitted to the ELSP or its
context completed. This ensures that context save is carried out before
the last request for a context is considered retireable. request_complete()
now checks the elsp_submitted count when deciding if a request is complete.
Requests that were not waiting for a context
switch interrupt (either as a result of being merged into a following
request or by being a legacy request) will be considered retireable as
soon as their seqno has passed.
Removed the extra request reference held for the execlist request.
Removed intel_execlists_retire_requests() and all references to
intel_engine_cs.execlist_retired_req_list.
Changed gen8_cs_irq_handler() so that notify_ring() is called when
contexts complete as well as when a user interrupt occurs so that
notification happens when a request is complete and context save has
finished.
v2: Rebase over the read-read optimisation changes
v3: Reworked IRQ handler after removing IRQ handler cleanup patch
v4: Fixed various pin leaks
v5: Removed ctx_complete flag & associated changes. Removed extraneous
request pin of context.
(Chris Wilson/Daniel Vetter)
Issue: VIZ-4277
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++---------
drivers/gpu/drm/i915/i915_irq.c | 7 ++---
drivers/gpu/drm/i915/intel_lrc.c | 45 ++++-----------------------------
drivers/gpu/drm/i915/intel_lrc.h | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
6 files changed, 21 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8afda45..ae08e57 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2914,7 +2914,7 @@ static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
seqno = req->ring->get_seqno(req->ring, lazy_coherency);
- return i915_seqno_passed(seqno, req->seqno);
+ return i915_seqno_passed(seqno, req->seqno) && !req->elsp_submitted;
}
int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e57061a..290a1ac 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2848,12 +2848,16 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
if (!list_empty(&obj->last_read_req[ring->id]->list))
break;
+ if (!i915_gem_request_completed(obj->last_read_req[ring->id],
+ true))
+ break;
i915_gem_object_retire__read(obj, ring->id);
}
if (unlikely(ring->trace_irq_req &&
- i915_gem_request_completed(ring->trace_irq_req, true))) {
+ i915_gem_request_completed(ring->trace_irq_req,
+ true))) {
ring->irq_put(ring);
i915_gem_request_assign(&ring->trace_irq_req, NULL);
}
@@ -2872,15 +2876,6 @@ i915_gem_retire_requests(struct drm_device *dev)
for_each_ring(ring, dev_priv, i) {
i915_gem_retire_requests_ring(ring);
idle &= list_empty(&ring->request_list);
- if (i915.enable_execlists) {
- unsigned long flags;
-
- spin_lock_irqsave(&ring->execlist_lock, flags);
- idle &= list_empty(&ring->execlist_queue);
- spin_unlock_irqrestore(&ring->execlist_lock, flags);
-
- intel_execlists_retire_requests(ring);
- }
}
if (idle)
@@ -2956,12 +2951,14 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
if (req == NULL)
continue;
- if (list_empty(&req->list))
- goto retire;
+ if (list_empty(&req->list)) {
+ if (i915_gem_request_completed(req, true))
+ i915_gem_object_retire__read(obj, i);
+ continue;
+ }
if (i915_gem_request_completed(req, true)) {
__i915_gem_request_retire__upto(req);
-retire:
i915_gem_object_retire__read(obj, i);
}
}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7837f5e..86a6662 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1294,10 +1294,11 @@ static __always_inline void
gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir,
int test_shift)
{
- if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
- notify_ring(ring);
+ bool need_notify = false;
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
- intel_lrc_irq_handler(ring);
+ need_notify = intel_lrc_irq_handler(ring);
+ if ((iir & (GT_RENDER_USER_INTERRUPT << test_shift)) || need_notify)
+ notify_ring(ring);
}
static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 88e12bd..8428ebd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -426,9 +426,8 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
/* Same ctx: ignore first request, as second request
* will update tail past first request's workload */
cursor->elsp_submitted = req0->elsp_submitted;
+ req0->elsp_submitted = 0;
list_del(&req0->execlist_link);
- list_add_tail(&req0->execlist_link,
- &ring->execlist_retired_req_list);
req0 = cursor;
} else {
req1 = cursor;
@@ -478,11 +477,8 @@ static bool execlists_check_remove_request(struct intel_engine_cs *ring,
if (intel_execlists_ctx_id(ctx_obj) == request_id) {
WARN(head_req->elsp_submitted == 0,
"Never submitted head request\n");
-
if (--head_req->elsp_submitted <= 0) {
list_del(&head_req->execlist_link);
- list_add_tail(&head_req->execlist_link,
- &ring->execlist_retired_req_list);
return true;
}
}
@@ -497,8 +493,9 @@ static bool execlists_check_remove_request(struct intel_engine_cs *ring,
*
* Check the unread Context Status Buffers and manage the submission of new
* contexts to the ELSP accordingly.
+ * @return whether a context completed
*/
-void intel_lrc_irq_handler(struct intel_engine_cs *ring)
+bool intel_lrc_irq_handler(struct intel_engine_cs *ring)
{
struct drm_i915_private *dev_priv = ring->dev->dev_private;
u32 status_pointer;
@@ -558,6 +555,8 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
_MASKED_FIELD(GEN8_CSB_PTR_MASK << 8,
((u32)ring->next_context_status_buffer &
GEN8_CSB_PTR_MASK) << 8));
+
+ return (submit_contexts != 0);
}
static int execlists_context_queue(struct drm_i915_gem_request *request)
@@ -566,11 +565,6 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
struct drm_i915_gem_request *cursor;
int num_elements = 0;
- if (request->ctx != ring->default_context)
- intel_lr_context_pin(request);
-
- i915_gem_request_reference(request);
-
spin_lock_irq(&ring->execlist_lock);
list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
@@ -588,8 +582,6 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
WARN(tail_req->elsp_submitted != 0,
"More than 2 already-submitted reqs queued\n");
list_del(&tail_req->execlist_link);
- list_add_tail(&tail_req->execlist_link,
- &ring->execlist_retired_req_list);
}
}
@@ -943,32 +935,6 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
return 0;
}
-void intel_execlists_retire_requests(struct intel_engine_cs *ring)
-{
- struct drm_i915_gem_request *req, *tmp;
- struct list_head retired_list;
-
- WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
- if (list_empty(&ring->execlist_retired_req_list))
- return;
-
- INIT_LIST_HEAD(&retired_list);
- spin_lock_irq(&ring->execlist_lock);
- list_replace_init(&ring->execlist_retired_req_list, &retired_list);
- spin_unlock_irq(&ring->execlist_lock);
-
- list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
- struct intel_context *ctx = req->ctx;
- struct drm_i915_gem_object *ctx_obj =
- ctx->engine[ring->id].state;
-
- if (ctx_obj && (ctx != ring->default_context))
- intel_lr_context_unpin(req);
- list_del(&req->execlist_link);
- i915_gem_request_unreference(req);
- }
-}
-
void intel_logical_ring_stop(struct intel_engine_cs *ring)
{
struct drm_i915_private *dev_priv = ring->dev->dev_private;
@@ -1924,7 +1890,6 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
init_waitqueue_head(&ring->irq_queue);
INIT_LIST_HEAD(&ring->execlist_queue);
- INIT_LIST_HEAD(&ring->execlist_retired_req_list);
spin_lock_init(&ring->execlist_lock);
ret = i915_cmd_parser_init_ring(ring);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 4e60d54..e6a4900 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -95,7 +95,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
struct list_head *vmas);
u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
-void intel_lrc_irq_handler(struct intel_engine_cs *ring);
+bool intel_lrc_irq_handler(struct intel_engine_cs *ring);
void intel_execlists_retire_requests(struct intel_engine_cs *ring);
#endif /* _INTEL_LRC_H_ */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 49fa41d..d99b167 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -264,7 +264,6 @@ struct intel_engine_cs {
/* Execlists */
spinlock_t execlist_lock;
struct list_head execlist_queue;
- struct list_head execlist_retired_req_list;
u8 next_context_status_buffer;
u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
int (*emit_request)(struct drm_i915_gem_request *request);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/6] drm/i915: Unify execlist and legacy request life-cycles
2015-10-20 9:23 ` [PATCH 3/6] drm/i915: Unify execlist and legacy request life-cycles Nick Hoath
@ 2015-10-20 9:53 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2015-10-20 9:53 UTC (permalink / raw)
To: Nick Hoath; +Cc: intel-gfx, Daniel Vetter
On Tue, Oct 20, 2015 at 10:23:53AM +0100, Nick Hoath wrote:
> There is a desire to simplify the i915 driver by reducing the number of
> different code paths introduced by the LRC / execlists support. As the
> execlists request is now part of the gem request it is possible and
> desirable to unify the request life-cycles for execlist and legacy
> requests.
>
> A request is considered retireable if its seqno passed (i.e. the request
> has completed) and either it was never submitted to the ELSP or its
> context completed. This ensures that context save is carried out before
> the last request for a context is considered retireable. request_complete()
> now checks the elsp_submitted count when deciding if a request is complete.
> Requests that were not waiting for a context
> switch interrupt (either as a result of being merged into a following
> request or by being a legacy request) will be considered retireable as
> soon as their seqno has passed.
>
> Removed the extra request reference held for the execlist request.
>
> Removed intel_execlists_retire_requests() and all references to
> intel_engine_cs.execlist_retired_req_list.
>
> Changed gen8_cs_irq_handler() so that notify_ring() is called when
> contexts complete as well as when a user interrupt occurs so that
> notification happens when a request is complete and context save has
> finished.
>
> v2: Rebase over the read-read optimisation changes
>
> v3: Reworked IRQ handler after removing IRQ handler cleanup patch
>
> v4: Fixed various pin leaks
>
> v5: Removed ctx_complete flag & associated changes. Removed extraneous
> request pin of context.
> (Chris Wilson/Daniel Vetter)
>
> Issue: VIZ-4277
> Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 23 ++++++++---------
> drivers/gpu/drm/i915/i915_irq.c | 7 ++---
> drivers/gpu/drm/i915/intel_lrc.c | 45 ++++-----------------------------
> drivers/gpu/drm/i915/intel_lrc.h | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
> 6 files changed, 21 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8afda45..ae08e57 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2914,7 +2914,7 @@ static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
>
> seqno = req->ring->get_seqno(req->ring, lazy_coherency);
>
> - return i915_seqno_passed(seqno, req->seqno);
> + return i915_seqno_passed(seqno, req->seqno) && !req->elsp_submitted;
> }
>
> int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e57061a..290a1ac 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2848,12 +2848,16 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
>
> if (!list_empty(&obj->last_read_req[ring->id]->list))
> break;
> + if (!i915_gem_request_completed(obj->last_read_req[ring->id],
> + true))
> + break;
What???? No. request_completed is and should only ever be has the seqno
passed.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/6] drm/i915: Improve dynamic management/eviction of lrc backing objects
2015-10-20 9:23 [PATCH 0/6] lrc lifecycle cleanups Nick Hoath
` (2 preceding siblings ...)
2015-10-20 9:23 ` [PATCH 3/6] drm/i915: Unify execlist and legacy request life-cycles Nick Hoath
@ 2015-10-20 9:23 ` Nick Hoath
2015-10-20 9:54 ` Chris Wilson
2015-10-20 10:14 ` kbuild test robot
2015-10-20 9:23 ` [PATCH 5/6] drm/i915: Add the CPU mapping of the hw context to the pinned items Nick Hoath
2015-10-20 9:23 ` [PATCH 6/6] drm/i915: Only update ringbuf address when necessary Nick Hoath
5 siblings, 2 replies; 13+ messages in thread
From: Nick Hoath @ 2015-10-20 9:23 UTC (permalink / raw)
To: intel-gfx
Shovel all context related objects through the active queue and obj
management.
- Added callback in vma_(un)bind to add CPU (un)mapping at same time
if desired
- Inserted LRC hw context & ringbuf to vma active list
Issue: VIZ-4277
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_gem.c | 3 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++
drivers/gpu/drm/i915/intel_lrc.c | 28 +++++++++++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 71 ++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 --
6 files changed, 79 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ae08e57..0dd4ace 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2161,6 +2161,10 @@ struct drm_i915_gem_object {
struct work_struct *work;
} userptr;
};
+
+ /** Support for automatic CPU side mapping of object */
+ int (*mmap)(struct drm_i915_gem_object *obj, bool unmap);
+ void *mappable;
};
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 290a1ac..8bd318a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3222,6 +3222,9 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
if (vma->pin_count)
return -EBUSY;
+ if (obj->mmap)
+ obj->mmap(obj, true);
+
BUG_ON(obj->pages == NULL);
if (wait) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 43f35d1..2812757 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3517,6 +3517,14 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
vma->bound |= bind_flags;
+ if (vma->obj->mmap) {
+ ret = vma->obj->mmap(vma->obj, false);
+ if (ret) {
+ i915_vma_unbind(vma);
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8428ebd..069950e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -719,6 +719,18 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
intel_logical_ring_advance(request->ringbuf);
+ /* Push the hw context on to the active list */
+ i915_vma_move_to_active(
+ i915_gem_obj_to_ggtt(
+ request->ctx->engine[ring->id].state),
+ request);
+
+ /* Push the ringbuf on to the active list */
+ i915_vma_move_to_active(
+ i915_gem_obj_to_ggtt(
+ request->ctx->engine[ring->id].ringbuf->obj),
+ request);
+
request->tail = request->ringbuf->tail;
if (intel_ring_stopped(ring))
@@ -987,10 +999,15 @@ static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
if (ret)
return ret;
- ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
+ ret = i915_gem_obj_ggtt_pin(ringbuf->obj, PAGE_SIZE,
+ PIN_MAPPABLE);
if (ret)
goto unpin_ctx_obj;
+ ret = i915_gem_object_set_to_gtt_domain(ringbuf->obj, true);
+ if (ret)
+ goto unpin_rb_obj;
+
ctx_obj->dirty = true;
/* Invalidate GuC TLB. */
@@ -999,6 +1016,8 @@ static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
return ret;
+unpin_rb_obj:
+ i915_gem_object_ggtt_unpin(ringbuf->obj);
unpin_ctx_obj:
i915_gem_object_ggtt_unpin(ctx_obj);
@@ -1033,7 +1052,7 @@ void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
if (ctx_obj) {
WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
if (--rq->ctx->engine[ring->id].pin_count == 0) {
- intel_unpin_ringbuffer_obj(ringbuf);
+ i915_gem_object_ggtt_unpin(ringbuf->obj);
i915_gem_object_ggtt_unpin(ctx_obj);
}
}
@@ -2351,7 +2370,7 @@ void intel_lr_context_free(struct intel_context *ctx)
struct intel_engine_cs *ring = ringbuf->ring;
if (ctx == ring->default_context) {
- intel_unpin_ringbuffer_obj(ringbuf);
+ i915_gem_object_ggtt_unpin(ringbuf->obj);
i915_gem_object_ggtt_unpin(ctx_obj);
}
WARN_ON(ctx->engine[ring->id].pin_count);
@@ -2518,5 +2537,8 @@ void intel_lr_context_reset(struct drm_device *dev,
ringbuf->head = 0;
ringbuf->tail = 0;
+
+ i915_gem_object_ggtt_unpin(
+ ctx->engine[ring->id].state);
}
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9461a23..e93a45c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2002,38 +2002,35 @@ static int init_phys_status_page(struct intel_engine_cs *ring)
return 0;
}
-void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
+static int intel_mmap_ringbuffer_obj(struct drm_i915_gem_object *obj,
+ bool unmap)
{
- iounmap(ringbuf->virtual_start);
- ringbuf->virtual_start = NULL;
- i915_gem_object_ggtt_unpin(ringbuf->obj);
-}
-
-int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
- struct intel_ringbuffer *ringbuf)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = ringbuf->obj;
- int ret;
-
- ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
- if (ret)
- return ret;
-
- ret = i915_gem_object_set_to_gtt_domain(obj, true);
- if (ret) {
- i915_gem_object_ggtt_unpin(obj);
- return ret;
- }
-
- ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
- i915_gem_obj_ggtt_offset(obj), ringbuf->size);
- if (ringbuf->virtual_start == NULL) {
- i915_gem_object_ggtt_unpin(obj);
- return -EINVAL;
+ int ret = 0;
+ struct intel_ringbuffer *ringbuf =
+ (struct intel_ringbuffer *)obj->mappable;
+
+ if (!unmap) {
+ struct drm_device *dev = ringbuf->ring->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ WARN_ON(ringbuf->virtual_start != NULL);
+ if (ringbuf->virtual_start == NULL) {
+ ringbuf->virtual_start = ioremap_wc(
+ dev_priv->gtt.mappable_base +
+ i915_gem_obj_ggtt_offset(obj),
+ ringbuf->size);
+ if (ringbuf->virtual_start == NULL) {
+ i915_gem_object_ggtt_unpin(obj);
+ return -EINVAL;
+ }
+ }
+ } else {
+ if (!i915_gem_obj_is_pinned(ringbuf->obj)) {
+ iounmap(ringbuf->virtual_start);
+ ringbuf->virtual_start = NULL;
+ }
}
-
- return 0;
+ return ret;
}
static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
@@ -2060,6 +2057,9 @@ static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
ringbuf->obj = obj;
+ obj->mmap = intel_mmap_ringbuffer_obj;
+ obj->mappable = ringbuf;
+
return 0;
}
@@ -2138,7 +2138,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
goto error;
}
- ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
+ ret = i915_gem_obj_ggtt_pin(ringbuf->obj, PAGE_SIZE, PIN_MAPPABLE);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
ring->name, ret);
@@ -2146,12 +2146,19 @@ static int intel_init_ring_buffer(struct drm_device *dev,
goto error;
}
+ ret = i915_gem_object_set_to_gtt_domain(ringbuf->obj, true);
+ if (ret)
+ goto error_unpin;
+
ret = i915_cmd_parser_init_ring(ring);
if (ret)
goto error;
return 0;
+error_unpin:
+ i915_gem_object_ggtt_unpin(ringbuf->obj);
+ intel_destroy_ringbuffer_obj(ringbuf);
error:
intel_ringbuffer_free(ringbuf);
ring->buffer = NULL;
@@ -2170,7 +2177,7 @@ void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
intel_stop_ring_buffer(ring);
WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
- intel_unpin_ringbuffer_obj(ring->buffer);
+ i915_gem_object_ggtt_unpin(ring->buffer->obj);
intel_ringbuffer_free(ring->buffer);
ring->buffer = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index d99b167..8daaf99 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -421,9 +421,6 @@ intel_write_status_page(struct intel_engine_cs *ring,
struct intel_ringbuffer *
intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
-int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
- struct intel_ringbuffer *ringbuf);
-void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
void intel_ringbuffer_free(struct intel_ringbuffer *ring);
void intel_stop_ring_buffer(struct intel_engine_cs *ring);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 4/6] drm/i915: Improve dynamic management/eviction of lrc backing objects
2015-10-20 9:23 ` [PATCH 4/6] drm/i915: Improve dynamic management/eviction of lrc backing objects Nick Hoath
@ 2015-10-20 9:54 ` Chris Wilson
2015-10-20 10:14 ` kbuild test robot
1 sibling, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2015-10-20 9:54 UTC (permalink / raw)
To: Nick Hoath; +Cc: intel-gfx
On Tue, Oct 20, 2015 at 10:23:54AM +0100, Nick Hoath wrote:
> Shovel all context related objects through the active queue and obj
> management.
>
> - Added callback in vma_(un)bind to add CPU (un)mapping at same time
> if desired
> - Inserted LRC hw context & ringbuf to vma active list
>
> Issue: VIZ-4277
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++
> drivers/gpu/drm/i915/i915_gem.c | 3 ++
> drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++
> drivers/gpu/drm/i915/intel_lrc.c | 28 +++++++++++--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 71 ++++++++++++++++++---------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 3 --
> 6 files changed, 79 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ae08e57..0dd4ace 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2161,6 +2161,10 @@ struct drm_i915_gem_object {
> struct work_struct *work;
> } userptr;
> };
> +
> + /** Support for automatic CPU side mapping of object */
> + int (*mmap)(struct drm_i915_gem_object *obj, bool unmap);
> + void *mappable;
> };
> #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 290a1ac..8bd318a 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3222,6 +3222,9 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
> if (vma->pin_count)
> return -EBUSY;
>
> + if (obj->mmap)
> + obj->mmap(obj, true);
This is not a per-obj callback.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 4/6] drm/i915: Improve dynamic management/eviction of lrc backing objects
2015-10-20 9:23 ` [PATCH 4/6] drm/i915: Improve dynamic management/eviction of lrc backing objects Nick Hoath
2015-10-20 9:54 ` Chris Wilson
@ 2015-10-20 10:14 ` kbuild test robot
1 sibling, 0 replies; 13+ messages in thread
From: kbuild test robot @ 2015-10-20 10:14 UTC (permalink / raw)
To: Nick Hoath; +Cc: intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1455 bytes --]
Hi Nick,
[auto build test WARNING on next-20151020 -- if it's inappropriate base, please suggest rules for selecting the more suitable base]
url: https://github.com/0day-ci/linux/commits/Nick-Hoath/lrc-lifecycle-cleanups/20151020-173347
config: i386-randconfig-x009-10191220 (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'i915_vma_bind':
>> drivers/gpu/drm/i915/i915_gem_gtt.c:3523:4: warning: ignoring return value of 'i915_vma_unbind', declared with attribute warn_unused_result [-Wunused-result]
i915_vma_unbind(vma);
^
vim +/i915_vma_unbind +3523 drivers/gpu/drm/i915/i915_gem_gtt.c
3507 vma->node.start,
3508 vma->node.size);
3509 vma->pin_count--;
3510 if (ret)
3511 return ret;
3512 }
3513
3514 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3515 if (ret)
3516 return ret;
3517
3518 vma->bound |= bind_flags;
3519
3520 if (vma->obj->mmap) {
3521 ret = vma->obj->mmap(vma->obj, false);
3522 if (ret) {
> 3523 i915_vma_unbind(vma);
3524 return ret;
3525 }
3526 }
3527
3528 return 0;
3529 }
3530
3531 /**
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 26282 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 5/6] drm/i915: Add the CPU mapping of the hw context to the pinned items.
2015-10-20 9:23 [PATCH 0/6] lrc lifecycle cleanups Nick Hoath
` (3 preceding siblings ...)
2015-10-20 9:23 ` [PATCH 4/6] drm/i915: Improve dynamic management/eviction of lrc backing objects Nick Hoath
@ 2015-10-20 9:23 ` Nick Hoath
2015-10-20 9:56 ` Chris Wilson
2015-10-20 9:23 ` [PATCH 6/6] drm/i915: Only update ringbuf address when necessary Nick Hoath
5 siblings, 1 reply; 13+ messages in thread
From: Nick Hoath @ 2015-10-20 9:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
Pin the hw ctx mapping so that it is not mapped/unmapped per bb
when doing GuC submission.
v2: Removed interim development extra mapping. (Daniel Vetter)
Issue: VIZ-4277
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Cc: David Gordon <david.s.gordon@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 ++++-------
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/intel_lrc.c | 46 ++++++++++++++++++++++++++-----------
3 files changed, 40 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a3b22bd..f0a172e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1970,10 +1970,9 @@ static int i915_context_status(struct seq_file *m, void *unused)
static void i915_dump_lrc_obj(struct seq_file *m,
struct intel_engine_cs *ring,
- struct drm_i915_gem_object *ctx_obj)
+ struct drm_i915_gem_object *ctx_obj,
+ uint32_t *reg_state)
{
- struct page *page;
- uint32_t *reg_state;
int j;
unsigned long ggtt_offset = 0;
@@ -1996,17 +1995,13 @@ static void i915_dump_lrc_obj(struct seq_file *m,
return;
}
- page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
- if (!WARN_ON(page == NULL)) {
- reg_state = kmap_atomic(page);
-
+ if (!WARN_ON(reg_state == NULL)) {
for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
ggtt_offset + 4096 + (j * 4),
reg_state[j], reg_state[j + 1],
reg_state[j + 2], reg_state[j + 3]);
}
- kunmap_atomic(reg_state);
}
seq_putc(m, '\n');
@@ -2034,7 +2029,8 @@ static int i915_dump_lrc(struct seq_file *m, void *unused)
for_each_ring(ring, dev_priv, i) {
if (ring->default_context != ctx)
i915_dump_lrc_obj(m, ring,
- ctx->engine[i].state);
+ ctx->engine[i].state,
+ ctx->engine[i].reg_state);
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0dd4ace..dc69d67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -881,8 +881,10 @@ struct intel_context {
} legacy_hw_ctx;
/* Execlists */
- struct {
+ struct intel_context_engine {
struct drm_i915_gem_object *state;
+ uint32_t *reg_state;
+ struct page *page;
struct intel_ringbuffer *ringbuf;
int pin_count;
} engine[I915_NUM_RINGS];
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 069950e..a35efcd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -360,16 +360,13 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
- struct page *page;
- uint32_t *reg_state;
+ uint32_t *reg_state = rq->ctx->engine[ring->id].reg_state;
BUG_ON(!ctx_obj);
+ WARN_ON(!reg_state);
WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
- page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
- reg_state = kmap_atomic(page);
-
reg_state[CTX_RING_TAIL+1] = rq->tail;
reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
@@ -385,8 +382,6 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
}
- kunmap_atomic(reg_state);
-
return 0;
}
@@ -985,7 +980,31 @@ int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
return 0;
}
-static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
+static int intel_mmap_hw_context(struct drm_i915_gem_object *obj,
+ bool unmap)
+{
+ int ret = 0;
+ struct intel_context_engine *ice =
+ (struct intel_context_engine *)obj->mappable;
+ struct page *page;
+ uint32_t *reg_state;
+
+ if (unmap) {
+ kunmap(ice->page);
+ ice->reg_state = NULL;
+ ice->page = NULL;
+ } else {
+ page = i915_gem_object_get_page(obj, LRC_STATE_PN);
+ reg_state = kmap(page);
+ ice->reg_state = reg_state;
+ ice->page = page;
+ }
+ return ret;
+}
+
+static int intel_lr_context_do_pin(
+ struct intel_context *ctx,
+ struct intel_engine_cs *ring,
struct drm_i915_gem_object *ctx_obj,
struct intel_ringbuffer *ringbuf)
{
@@ -1032,7 +1051,7 @@ static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
struct intel_ringbuffer *ringbuf = rq->ringbuf;
if (rq->ctx->engine[ring->id].pin_count++ == 0) {
- ret = intel_lr_context_do_pin(ring, ctx_obj, ringbuf);
+ ret = intel_lr_context_do_pin(rq->ctx, ring, ctx_obj, ringbuf);
if (ret)
goto reset_pin_count;
}
@@ -1921,6 +1940,7 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
/* As this is the default context, always pin it */
ret = intel_lr_context_do_pin(
+ ring->default_context,
ring,
ring->default_context->engine[ring->id].state,
ring->default_context->engine[ring->id].ringbuf);
@@ -2471,6 +2491,8 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
goto error_ringbuf;
}
+ ctx_obj->mmap = intel_mmap_hw_context;
+ ctx_obj->mappable = &(ctx->engine[ring->id]);
ctx->engine[ring->id].ringbuf = ringbuf;
ctx->engine[ring->id].state = ctx_obj;
@@ -2518,7 +2540,6 @@ void intel_lr_context_reset(struct drm_device *dev,
struct intel_ringbuffer *ringbuf =
ctx->engine[ring->id].ringbuf;
uint32_t *reg_state;
- struct page *page;
if (!ctx_obj)
continue;
@@ -2527,14 +2548,11 @@ void intel_lr_context_reset(struct drm_device *dev,
WARN(1, "Failed get_pages for context obj\n");
continue;
}
- page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
- reg_state = kmap_atomic(page);
+ reg_state = ctx->engine[ring->id].reg_state;
reg_state[CTX_RING_HEAD+1] = 0;
reg_state[CTX_RING_TAIL+1] = 0;
- kunmap_atomic(reg_state);
-
ringbuf->head = 0;
ringbuf->tail = 0;
--
1.9.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 6/6] drm/i915: Only update ringbuf address when necessary
2015-10-20 9:23 [PATCH 0/6] lrc lifecycle cleanups Nick Hoath
` (4 preceding siblings ...)
2015-10-20 9:23 ` [PATCH 5/6] drm/i915: Add the CPU mapping of the hw context to the pinned items Nick Hoath
@ 2015-10-20 9:23 ` Nick Hoath
5 siblings, 0 replies; 13+ messages in thread
From: Nick Hoath @ 2015-10-20 9:23 UTC (permalink / raw)
To: intel-gfx
We now only need to update the address of the ringbuf object in the
hw context when it is pinned, and the hw context is first CPU mapped
Issue: VIZ-4277
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Cc: David Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a35efcd..2e529a4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -368,7 +368,6 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
reg_state[CTX_RING_TAIL+1] = rq->tail;
- reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
/* True 32b PPGTT with dynamic page allocation: update PDP
@@ -1027,6 +1026,9 @@ static int intel_lr_context_do_pin(
if (ret)
goto unpin_rb_obj;
+ ctx->engine[ring->id].reg_state[CTX_RING_BUFFER_START+1] =
+ i915_gem_obj_ggtt_offset(ringbuf->obj);
+
ctx_obj->dirty = true;
/* Invalidate GuC TLB. */
--
1.9.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread