[PATCH 1/7] drm/i915/skl: Print the DMC firmware status in debugfs

[PATCH 1/7] drm/i915/skl: Print the DMC firmware status in debugfs

[Mika Kuoppala]

From: Damien Lespiau <damien.lespiau@intel.com>

Create a new debufs file for it, we'll have a few more things to add
there.

v2: Fix checkpatch warning about static const array

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a3b22bd..ceae425 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2777,6 +2777,27 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_dmc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum csr_state csr_state;
+	static const char * const csr_state_str[] = {
+		"unknown", "loaded", "error"
+	};
+
+	if (!HAS_CSR(dev)) {
+		seq_puts(m, "not supported\n");
+		return 0;
+	}
+
+	csr_state = intel_csr_load_status_get(dev_priv);
+	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
+
+	return 0;
+}
+
 static void intel_seq_print_mode(struct seq_file *m, int tabs,
 				 struct drm_display_mode *mode)
 {
@@ -5236,6 +5257,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_energy_uJ", i915_energy_uJ, 0},
 	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
 	{"i915_power_domain_info", i915_power_domain_info, 0},
+	{"i915_dmc_info", i915_dmc_info, 0},
 	{"i915_display_info", i915_display_info, 0},
 	{"i915_semaphore_status", i915_semaphore_status, 0},
 	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
-- 
2.1.4

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[PATCH 2/7] drm/i915/skl: Store and print the DMC firmware version we load

[Mika Kuoppala]

From: Damien Lespiau <damien.lespiau@intel.com>

That can be handy later on to tell which DMC firmware version the user
has, by just looking at the dmesg or a debugfs file.

v2: use DRM_DEBUG_DRIVER (Chris)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
 drivers/gpu/drm/i915/i915_drv.h     | 5 +++++
 drivers/gpu/drm/i915/intel_csr.c    | 9 ++++++++-
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ceae425..7a0592b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2782,6 +2782,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	struct drm_info_node *node = m->private;
 	struct drm_device *dev = node->minor->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_csr *csr = &dev_priv->csr;
 	enum csr_state csr_state;
 	static const char * const csr_state_str[] = {
 		"unknown", "loaded", "error"
@@ -2795,6 +2796,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	csr_state = intel_csr_load_status_get(dev_priv);
 	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
 
+	if (csr_state != FW_LOADED)
+		return 0;
+
+	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
+		   CSR_VERSION_MINOR(csr->version));
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48a742c..1b1a989 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -736,6 +736,10 @@ struct intel_uncore {
 #define for_each_fw_domain(domain__, dev_priv__, i__) \
 	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
 
+#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
+#define CSR_VERSION_MAJOR(version)	((version) >> 16)
+#define CSR_VERSION_MINOR(version)	((version) & 0xffff)
+
 enum csr_state {
 	FW_UNINITIALIZED = 0,
 	FW_LOADED,
@@ -746,6 +750,7 @@ struct intel_csr {
 	const char *fw_path;
 	uint32_t *dmc_payload;
 	uint32_t dmc_fw_size;
+	uint32_t version;
 	uint32_t mmio_count;
 	uint32_t mmioaddr[8];
 	uint32_t mmiodata[8];
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 9e530a7..cabcc51 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -321,6 +321,9 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 			(css_header->header_len * 4));
 		goto out;
 	}
+
+	csr->version = css_header->version;
+
 	readcount += sizeof(struct intel_css_header);
 
 	/* Extract Package Header information*/
@@ -402,7 +405,11 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	intel_csr_load_program(dev);
 	fw_loaded = true;
 
-	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
+	DRM_DEBUG_DRIVER("Finished loading %s (v%d.%d)\n",
+			 dev_priv->csr.fw_path,
+			 CSR_VERSION_MAJOR(csr->version),
+			 CSR_VERSION_MINOR(csr->version));
+
 out:
 	if (fw_loaded)
 		intel_runtime_pm_put(dev_priv);
-- 
2.1.4

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[PATCH 3/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Mika Kuoppala]

There is known issue on GT interrupt delivery with DC6 and
firmwares <1.21. There is a suspicion that this causes
spurious gpu hangs on driver init and with some workloads,
as upgrading the firmware to 1.21 makes these problems
disappear.

As of now the current version included in distribution
firmware packages is very like to be 1.19. Play it safe and
refuse to load a firmware version that may affect gpu
side stability.

With < 1.23 there is a palette and dmc ram corruption issue
so blacklist anything below that.

v2: Refuse to load fw instead of notifying the user
v3: Rebase on header version changes
v4: Refuse to load anything less than 1.23

Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
References: https://01.org/linuxgraphics/downloads/skldmcver121
References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
Testcase: igt/gem_exec_nop
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index cabcc51..85261d4 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -47,6 +47,9 @@
 MODULE_FIRMWARE(I915_CSR_SKL);
 MODULE_FIRMWARE(I915_CSR_BXT);
 
+#define SKL_REQUIRED_FW_MAJOR	1
+#define SKL_REQUIRED_FW_MINOR	23
+
 /*
 * SKL CSR registers for DC5 and DC6
 */
@@ -401,6 +404,14 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	dmc_payload = csr->dmc_payload;
 	memcpy(dmc_payload, &fw->data[readcount], nbytes);
 
+	if (IS_SKYLAKE(dev) &&
+	    (CSR_VERSION_MAJOR(csr->version) < SKL_REQUIRED_FW_MAJOR ||
+	     CSR_VERSION_MINOR(csr->version) < SKL_REQUIRED_FW_MINOR)) {
+		DRM_INFO("Outdated dmc firmware found, please upgrade to %u.%u or newer\n",
+			 SKL_REQUIRED_FW_MAJOR, SKL_REQUIRED_FW_MINOR);
+		goto out;
+	}
+
 	/* load csr program during system boot, as needed for DC states */
 	intel_csr_load_program(dev);
 	fw_loaded = true;
-- 
2.1.4

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Re: [PATCH 3/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Chris Wilson]

On Wed, Oct 21, 2015 at 06:41:48PM +0300, Mika Kuoppala wrote:
> There is known issue on GT interrupt delivery with DC6 and
> firmwares <1.21. There is a suspicion that this causes
> spurious gpu hangs on driver init and with some workloads,
> as upgrading the firmware to 1.21 makes these problems
> disappear.
> 
> As of now the current version included in distribution
> firmware packages is very like to be 1.19. Play it safe and
> refuse to load a firmware version that may affect gpu
> side stability.
> 
> With < 1.23 there is a palette and dmc ram corruption issue
> so blacklist anything below that.
> 
> v2: Refuse to load fw instead of notifying the user
> v3: Rebase on header version changes
> v4: Refuse to load anything less than 1.23
> 
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> References: https://01.org/linuxgraphics/downloads/skldmcver121
> References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
> Testcase: igt/gem_exec_nop
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_csr.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index cabcc51..85261d4 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -47,6 +47,9 @@
>  MODULE_FIRMWARE(I915_CSR_SKL);
>  MODULE_FIRMWARE(I915_CSR_BXT);
>  
> +#define SKL_REQUIRED_FW_MAJOR	1
> +#define SKL_REQUIRED_FW_MINOR	23
> +
>  /*
>  * SKL CSR registers for DC5 and DC6
>  */
> @@ -401,6 +404,14 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  	dmc_payload = csr->dmc_payload;
>  	memcpy(dmc_payload, &fw->data[readcount], nbytes);
>  
> +	if (IS_SKYLAKE(dev) &&
> +	    (CSR_VERSION_MAJOR(csr->version) < SKL_REQUIRED_FW_MAJOR ||
> +	     CSR_VERSION_MINOR(csr->version) < SKL_REQUIRED_FW_MINOR)) {
> +		DRM_INFO("Outdated dmc firmware found, please upgrade to %u.%u or newer\n",
> +			 SKL_REQUIRED_FW_MAJOR, SKL_REQUIRED_FW_MINOR);

Please include the filename that should be updated. The first think the
user will do is copy-and-paste it into google, so we need to provide
enough information for the search results to return the right package.
-Chris

-- 
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[PATCH 3/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Mika Kuoppala]

There is known issue on GT interrupt delivery with DC6 and
firmwares <1.21. There is a suspicion that this causes
spurious gpu hangs on driver init and with some workloads,
as upgrading the firmware to 1.21 makes these problems
disappear.

As of now the current version included in distribution
firmware packages is very like to be 1.19. Play it safe and
refuse to load a firmware version that may affect gpu
side stability.

With < 1.23 there is a palette and dmc ram corruption issue
so blacklist anything below that.

v2: Refuse to load fw instead of notifying the user
v3: Rebase on header version changes
v4: Refuse to load anything less than 1.23
v5: Give enough information for user for finding correct fw (Chris)

Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
References: https://01.org/linuxgraphics/downloads/skldmcver121
References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
Testcase: igt/gem_exec_nop
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index cabcc51..8004b6d 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -47,6 +47,9 @@
 MODULE_FIRMWARE(I915_CSR_SKL);
 MODULE_FIRMWARE(I915_CSR_BXT);
 
+#define SKL_REQUIRED_FW_MAJOR	1
+#define SKL_REQUIRED_FW_MINOR	23
+
 /*
 * SKL CSR registers for DC5 and DC6
 */
@@ -401,6 +404,18 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	dmc_payload = csr->dmc_payload;
 	memcpy(dmc_payload, &fw->data[readcount], nbytes);
 
+	if (IS_SKYLAKE(dev) &&
+	    (CSR_VERSION_MAJOR(csr->version) < SKL_REQUIRED_FW_MAJOR ||
+	     CSR_VERSION_MINOR(csr->version) < SKL_REQUIRED_FW_MINOR)) {
+		DRM_INFO("Refusing to load outdated DMC firmware v%u.%u\n",
+			 CSR_VERSION_MAJOR(csr->version),
+			 CSR_VERSION_MINOR(csr->version));
+		DRM_INFO("Please upgrade to Skylake DMC - %u.%u or newer\n",
+			 SKL_REQUIRED_FW_MAJOR, SKL_REQUIRED_FW_MINOR);
+		DRM_INFO("https://01.org/linuxgraphics/downloads\n");
+		goto out;
+	}
+
 	/* load csr program during system boot, as needed for DC states */
 	intel_csr_load_program(dev);
 	fw_loaded = true;
-- 
2.1.4

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Re: [PATCH 3/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Chris Wilson]

On Thu, Oct 22, 2015 at 04:31:01PM +0300, Mika Kuoppala wrote:
> There is known issue on GT interrupt delivery with DC6 and
> firmwares <1.21. There is a suspicion that this causes
> spurious gpu hangs on driver init and with some workloads,
> as upgrading the firmware to 1.21 makes these problems
> disappear.
> 
> As of now the current version included in distribution
> firmware packages is very like to be 1.19. Play it safe and
> refuse to load a firmware version that may affect gpu
> side stability.
> 
> With < 1.23 there is a palette and dmc ram corruption issue
> so blacklist anything below that.
> 
> v2: Refuse to load fw instead of notifying the user
> v3: Rebase on header version changes
> v4: Refuse to load anything less than 1.23
> v5: Give enough information for user for finding correct fw (Chris)
> 
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> References: https://01.org/linuxgraphics/downloads/skldmcver121
> References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
> Testcase: igt/gem_exec_nop
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_csr.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index cabcc51..8004b6d 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -47,6 +47,9 @@
>  MODULE_FIRMWARE(I915_CSR_SKL);
>  MODULE_FIRMWARE(I915_CSR_BXT);
>  
> +#define SKL_REQUIRED_FW_MAJOR	1
> +#define SKL_REQUIRED_FW_MINOR	23
> +
>  /*
>  * SKL CSR registers for DC5 and DC6
>  */
> @@ -401,6 +404,18 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  	dmc_payload = csr->dmc_payload;
>  	memcpy(dmc_payload, &fw->data[readcount], nbytes);
>  
> +	if (IS_SKYLAKE(dev) &&
> +	    (CSR_VERSION_MAJOR(csr->version) < SKL_REQUIRED_FW_MAJOR ||
> +	     CSR_VERSION_MINOR(csr->version) < SKL_REQUIRED_FW_MINOR)) {
> +		DRM_INFO("Refusing to load outdated DMC firmware v%u.%u\n",
> +			 CSR_VERSION_MAJOR(csr->version),
> +			 CSR_VERSION_MINOR(csr->version));
> +		DRM_INFO("Please upgrade to Skylake DMC - %u.%u or newer\n",
> +			 SKL_REQUIRED_FW_MAJOR, SKL_REQUIRED_FW_MINOR);
> +		DRM_INFO("https://01.org/linuxgraphics/downloads\n");

Just what I mentioned on IRC, I think it is best if this is presented to
the user as a single info block *, and perhaps
https://01.org/linuxgraphics/intel-linux-graphics-firmwares
is a slightly more useful link?

* "Refusing to load old Skylake DMC firmware v%u.%u,"
" please upgrade to %u.%u or later"
" [https://01.org/linuxgraphics/intel-linux-graphics-firmwares]."
-Chris

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Re: [PATCH 3/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Chris Wilson]

On Thu, Oct 22, 2015 at 02:48:31PM +0100, Chris Wilson wrote:
> On Thu, Oct 22, 2015 at 04:31:01PM +0300, Mika Kuoppala wrote:
> > There is known issue on GT interrupt delivery with DC6 and
> > firmwares <1.21. There is a suspicion that this causes
> > spurious gpu hangs on driver init and with some workloads,
> > as upgrading the firmware to 1.21 makes these problems
> > disappear.
> > 
> > As of now the current version included in distribution
> > firmware packages is very like to be 1.19. Play it safe and
> > refuse to load a firmware version that may affect gpu
> > side stability.
> > 
> > With < 1.23 there is a palette and dmc ram corruption issue
> > so blacklist anything below that.
> > 
> > v2: Refuse to load fw instead of notifying the user
> > v3: Rebase on header version changes
> > v4: Refuse to load anything less than 1.23
> > v5: Give enough information for user for finding correct fw (Chris)
> > 
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Dave Gordon <david.s.gordon@intel.com>
> > Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > References: https://01.org/linuxgraphics/downloads/skldmcver121
> > References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
> > Testcase: igt/gem_exec_nop
> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_csr.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > index cabcc51..8004b6d 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -47,6 +47,9 @@
> >  MODULE_FIRMWARE(I915_CSR_SKL);
> >  MODULE_FIRMWARE(I915_CSR_BXT);
> >  
> > +#define SKL_REQUIRED_FW_MAJOR	1
> > +#define SKL_REQUIRED_FW_MINOR	23
> > +
> >  /*
> >  * SKL CSR registers for DC5 and DC6
> >  */
> > @@ -401,6 +404,18 @@ static void finish_csr_load(const struct firmware *fw, void *context)
> >  	dmc_payload = csr->dmc_payload;
> >  	memcpy(dmc_payload, &fw->data[readcount], nbytes);
> >  
> > +	if (IS_SKYLAKE(dev) &&
> > +	    (CSR_VERSION_MAJOR(csr->version) < SKL_REQUIRED_FW_MAJOR ||
> > +	     CSR_VERSION_MINOR(csr->version) < SKL_REQUIRED_FW_MINOR)) {
> > +		DRM_INFO("Refusing to load outdated DMC firmware v%u.%u\n",
> > +			 CSR_VERSION_MAJOR(csr->version),
> > +			 CSR_VERSION_MINOR(csr->version));
> > +		DRM_INFO("Please upgrade to Skylake DMC - %u.%u or newer\n",
> > +			 SKL_REQUIRED_FW_MAJOR, SKL_REQUIRED_FW_MINOR);
> > +		DRM_INFO("https://01.org/linuxgraphics/downloads\n");
> 
> Just what I mentioned on IRC, I think it is best if this is presented to
> the user as a single info block *, and perhaps
> https://01.org/linuxgraphics/intel-linux-graphics-firmwares
> is a slightly more useful link?
> 
> * "Refusing to load old Skylake DMC firmware v%u.%u,"
> " please upgrade to %u.%u or later"

Note we should be consistent with v%u.%u usage as well.
-Chris

-- 
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[PATCH 4/7] drm/i915/skl: Expose DC5/DC6 entry counts

[Mika Kuoppala]

From: Damien Lespiau <damien.lespiau@intel.com>

The CSR firmware expose two counters, handy to check if we are indeed
entering DC5/DC6.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
 drivers/gpu/drm/i915/i915_reg.h     | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7a0592b..d9440cc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2802,6 +2802,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
+	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
+		seq_printf(m, "DC3 -> DC5 count: %d\n",
+			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
+		seq_printf(m, "DC5 -> DC6 count: %d\n",
+			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ebf032..fb03892 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5696,6 +5696,10 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_12BIT	(2 << 0)
 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
+/* DMC/CSR */
+#define SKL_CSR_DC3_DC5_COUNT	0x80030
+#define SKL_CSR_DC5_DC6_COUNT	0x8002C
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.1.4

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Re: [PATCH 4/7] drm/i915/skl: Expose DC5/DC6 entry counts

[Rodrigo Vivi]

Do you know how to calculate a residency with these counters?
To be able to expose that through sysfs to powertop. Otherwise I
believe we should also expose the counters itself to powertop that
would be useful already.

Anyway, for this patch:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


On Wed, Oct 21, 2015 at 8:41 AM, Mika Kuoppala
<mika.kuoppala@linux.intel.com> wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
>
> The CSR firmware expose two counters, handy to check if we are indeed
> entering DC5/DC6.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h     | 4 ++++
>  2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7a0592b..d9440cc 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2802,6 +2802,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>                    CSR_VERSION_MINOR(csr->version));
>
> +       if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
> +               seq_printf(m, "DC3 -> DC5 count: %d\n",
> +                          I915_READ(SKL_CSR_DC3_DC5_COUNT));
> +               seq_printf(m, "DC5 -> DC6 count: %d\n",
> +                          I915_READ(SKL_CSR_DC5_DC6_COUNT));
> +       }
> +
>         return 0;
>  }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9ebf032..fb03892 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5696,6 +5696,10 @@ enum skl_disp_power_wells {
>  #define GAMMA_MODE_MODE_12BIT  (2 << 0)
>  #define GAMMA_MODE_MODE_SPLIT  (3 << 0)
>
> +/* DMC/CSR */
> +#define SKL_CSR_DC3_DC5_COUNT  0x80030
> +#define SKL_CSR_DC5_DC6_COUNT  0x8002C
> +
>  /* interrupts */
>  #define DE_MASTER_IRQ_CONTROL   (1 << 31)
>  #define DE_SPRITEB_FLIP_DONE    (1 << 29)
> --
> 2.1.4
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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Blog: http://blog.vivi.eng.br
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[PATCH 5/7] drm/i915/bxt: Expose DC5 entry count

[Mika Kuoppala]

For bxt CSR firmware exposes a count of dc5 entries. Expose
it through debugs

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d9440cc..5d606f0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2807,6 +2807,9 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
 			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+	} else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
+		seq_printf(m, "DC3 -> DC5 count: %d\n",
+			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb03892..05f4a18 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5699,6 +5699,7 @@ enum skl_disp_power_wells {
 /* DMC/CSR */
 #define SKL_CSR_DC3_DC5_COUNT	0x80030
 #define SKL_CSR_DC5_DC6_COUNT	0x8002C
+#define BXT_CSR_DC3_DC5_COUNT	0x80038
 
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
-- 
2.1.4

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[PATCH 6/7] drm/i915: Add dmc firmware load state and version to error state

[Mika Kuoppala]

We have had one case where buggy csr/dmc firmware version influenced
gt side and caused a hang. Add dmc firmware loading state and
version to error state.

v2: - Rebased on top of Damien's patches
    - included fw load state

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2f04e4f..5c1218f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -335,6 +335,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	struct drm_device *dev = error_priv->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_error_state *error = error_priv->error;
+	struct intel_csr *csr = &dev_priv->csr;
 	struct drm_i915_error_object *obj;
 	int i, j, offset, elt;
 	int max_hangcheck_score;
@@ -366,6 +367,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
 	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
+	err_printf(m, "DMC load state: %d\n", csr->state);
+	err_printf(m, "DMC fw version: %d.%d\n",
+		   CSR_VERSION_MAJOR(csr->version),
+		   CSR_VERSION_MINOR(csr->version));
 	err_printf(m, "EIR: 0x%08x\n", error->eir);
 	err_printf(m, "IER: 0x%08x\n", error->ier);
 	if (INTEL_INFO(dev)->gen >= 8) {
-- 
2.1.4

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Re: [PATCH 6/7] drm/i915: Add dmc firmware load state and version to error state

[Chris Wilson]

On Wed, Oct 21, 2015 at 06:41:51PM +0300, Mika Kuoppala wrote:
> We have had one case where buggy csr/dmc firmware version influenced
> gt side and caused a hang. Add dmc firmware loading state and
> version to error state.
> 
> v2: - Rebased on top of Damien's patches
>     - included fw load state
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2f04e4f..5c1218f 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -335,6 +335,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  	struct drm_device *dev = error_priv->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_i915_error_state *error = error_priv->error;
> +	struct intel_csr *csr = &dev_priv->csr;
>  	struct drm_i915_error_object *obj;
>  	int i, j, offset, elt;
>  	int max_hangcheck_score;
> @@ -366,6 +367,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  	err_printf(m, "Suspend count: %u\n", error->suspend_count);
>  	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
>  	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
> +	err_printf(m, "DMC load state: %d\n", csr->state);
> +	err_printf(m, "DMC fw version: %d.%d\n",
> +		   CSR_VERSION_MAJOR(csr->version),
> +		   CSR_VERSION_MINOR(csr->version));

I guess these are only interesting on platforms where we even have DMC,
and potentially confusing otherwise.
-Chris

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[PATCH 6/7] drm/i915: Add dmc firmware load state and version to error state

[Mika Kuoppala]

We have had one case where buggy csr/dmc firmware version influenced
gt side and caused a hang. Add dmc firmware loading state and
version to error state.

v2: - Rebased on top of Damien's patches
    - included fw load state
v3: include dmc info only if platform supports it

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2f04e4f..0735f40 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -335,6 +335,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	struct drm_device *dev = error_priv->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_error_state *error = error_priv->error;
+	struct intel_csr *csr = &dev_priv->csr;
 	struct drm_i915_error_object *obj;
 	int i, j, offset, elt;
 	int max_hangcheck_score;
@@ -366,6 +367,12 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
 	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
+	if (HAS_CSR(dev)) {
+		err_printf(m, "DMC load state: %d\n", csr->state);
+		err_printf(m, "DMC fw version: %d.%d\n",
+			   CSR_VERSION_MAJOR(csr->version),
+			   CSR_VERSION_MINOR(csr->version));
+	}
 	err_printf(m, "EIR: 0x%08x\n", error->eir);
 	err_printf(m, "IER: 0x%08x\n", error->ier);
 	if (INTEL_INFO(dev)->gen >= 8) {
-- 
2.1.4

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Re: [PATCH 6/7] drm/i915: Add dmc firmware load state and version to error state

[Chris Wilson]

On Thu, Oct 22, 2015 at 04:32:03PM +0300, Mika Kuoppala wrote:
> We have had one case where buggy csr/dmc firmware version influenced
> gt side and caused a hang. Add dmc firmware loading state and
> version to error state.
> 
> v2: - Rebased on top of Damien's patches
>     - included fw load state
> v3: include dmc info only if platform supports it
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2f04e4f..0735f40 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -335,6 +335,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  	struct drm_device *dev = error_priv->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_i915_error_state *error = error_priv->error;
> +	struct intel_csr *csr = &dev_priv->csr;
>  	struct drm_i915_error_object *obj;
>  	int i, j, offset, elt;
>  	int max_hangcheck_score;
> @@ -366,6 +367,12 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  	err_printf(m, "Suspend count: %u\n", error->suspend_count);
>  	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
>  	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
> +	if (HAS_CSR(dev)) {

if (HAS_CSR(dev_priv)) {
struct intel_csr *csr = &dev_priv->csr;

> +		err_printf(m, "DMC load state: %d\n", csr->state);
> +		err_printf(m, "DMC fw version: %d.%d\n",
> +			   CSR_VERSION_MAJOR(csr->version),
> +			   CSR_VERSION_MINOR(csr->version));
> +	}

and with that
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
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[PATCH 7/7] drm/i915: Add csr programming registers to dmc debugfs entry

[Mika Kuoppala]

We check these to determine firmware loading status. Include
them to help to debug causes of firmware loading fails.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++
 drivers/gpu/drm/i915/i915_reg.h     | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5d606f0..e54f1bf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2795,6 +2795,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
 	csr_state = intel_csr_load_status_get(dev_priv);
 	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
+	seq_printf(m, "path: %s\n", csr->fw_path);
+	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
+	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
+	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
 
 	if (csr_state != FW_LOADED)
 		return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 05f4a18..9966bfd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5697,6 +5697,9 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
 /* DMC/CSR */
+#define CSR_PROGRAM(i)		(0x80000 + (i) * 4)
+#define CSR_SSP_BASE		0x8F074
+#define CSR_HTP_SKL		0x8F004
 #define SKL_CSR_DC3_DC5_COUNT	0x80030
 #define SKL_CSR_DC5_DC6_COUNT	0x8002C
 #define BXT_CSR_DC3_DC5_COUNT	0x80038
-- 
2.1.4

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Re: [PATCH 7/7] drm/i915: Add csr programming registers to dmc debugfs entry

[Ville Syrjälä]

On Wed, Oct 21, 2015 at 06:41:52PM +0300, Mika Kuoppala wrote:
> We check these to determine firmware loading status. Include
> them to help to debug causes of firmware loading fails.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++
>  drivers/gpu/drm/i915/i915_reg.h     | 3 +++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5d606f0..e54f1bf 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2795,6 +2795,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  
>  	csr_state = intel_csr_load_status_get(dev_priv);
>  	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
> +	seq_printf(m, "path: %s\n", csr->fw_path);
> +	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
> +	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
> +	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
>  
>  	if (csr_state != FW_LOADED)
>  		return 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 05f4a18..9966bfd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5697,6 +5697,9 @@ enum skl_disp_power_wells {
>  #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
>  
>  /* DMC/CSR */
> +#define CSR_PROGRAM(i)		(0x80000 + (i) * 4)
> +#define CSR_SSP_BASE		0x8F074
> +#define CSR_HTP_SKL		0x8F004

Can you just move all of it from intel_csr.c to here?

>  #define SKL_CSR_DC3_DC5_COUNT	0x80030
>  #define SKL_CSR_DC5_DC6_COUNT	0x8002C
>  #define BXT_CSR_DC3_DC5_COUNT	0x80038
> -- 
> 2.1.4
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
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[PATCH 7/7] drm/i915: Add csr programming registers to dmc debugfs entry

[Mika Kuoppala]

We check these to determine firmware loading status. Include
them to help to debug causes of firmware loading fails.

v2: Move all CSR specific registers to i915_reg.h (Ville)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  4 ++++
 drivers/gpu/drm/i915/i915_reg.h     | 10 ++++++++++
 drivers/gpu/drm/i915/intel_csr.c    | 13 -------------
 3 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 859e62a..16fa5c1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2801,6 +2801,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
 	csr_state = intel_csr_load_status_get(dev_priv);
 	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
+	seq_printf(m, "path: %s\n", csr->fw_path);
+	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
+	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
+	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
 
 	if (csr_state != FW_LOADED)
 		return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 05f4a18..19b9e32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5697,6 +5697,16 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
 /* DMC/CSR */
+#define CSR_PROGRAM(i)		(0x80000 + (i) * 4)
+#define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
+#define CSR_HTP_ADDR_SKL	0x00500034
+#define CSR_SSP_BASE		0x8F074
+#define CSR_HTP_SKL		0x8F004
+#define CSR_LAST_WRITE		0x8F034
+#define CSR_LAST_WRITE_VALUE	0xc003b400
+/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
+#define CSR_MMIO_START_RANGE	0x80000
+#define CSR_MMIO_END_RANGE	0x8FFFF
 #define SKL_CSR_DC3_DC5_COUNT	0x80030
 #define SKL_CSR_DC5_DC6_COUNT	0x8002C
 #define BXT_CSR_DC3_DC5_COUNT	0x80038
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 8004b6d..2fb6f63 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -50,21 +50,8 @@ MODULE_FIRMWARE(I915_CSR_BXT);
 #define SKL_REQUIRED_FW_MAJOR	1
 #define SKL_REQUIRED_FW_MINOR	23
 
-/*
-* SKL CSR registers for DC5 and DC6
-*/
-#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
-#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
-#define CSR_HTP_ADDR_SKL		0x00500034
-#define CSR_SSP_BASE			0x8F074
-#define CSR_HTP_SKL			0x8F004
-#define CSR_LAST_WRITE			0x8F034
-#define CSR_LAST_WRITE_VALUE		0xc003b400
-/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
 #define CSR_MAX_FW_SIZE			0x2FFF
 #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
-#define CSR_MMIO_START_RANGE	0x80000
-#define CSR_MMIO_END_RANGE		0x8FFFF
 
 struct intel_css_header {
 	/* 0x09 for DMC */
-- 
2.1.4

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Re: [PATCH 1/7] drm/i915/skl: Print the DMC firmware status in debugfs

[Ville Syrjälä]

On Wed, Oct 21, 2015 at 06:41:46PM +0300, Mika Kuoppala wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> Create a new debufs file for it, we'll have a few more things to add
> there.
> 
> v2: Fix checkpatch warning about static const array
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a3b22bd..ceae425 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2777,6 +2777,27 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
>  	return 0;
>  }
>  
> +static int i915_dmc_info(struct seq_file *m, void *unused)
> +{
> +	struct drm_info_node *node = m->private;
> +	struct drm_device *dev = node->minor->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum csr_state csr_state;
> +	static const char * const csr_state_str[] = {
> +		"unknown", "loaded", "error"
> +	};

I'd use named initializers here. With that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
> +	if (!HAS_CSR(dev)) {
> +		seq_puts(m, "not supported\n");
> +		return 0;
> +	}
> +
> +	csr_state = intel_csr_load_status_get(dev_priv);

A side note: intel_csr_load_status_get() seems pretty useless. The lock
is protecting a single variable read.

> +	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
> +
> +	return 0;
> +}
> +
>  static void intel_seq_print_mode(struct seq_file *m, int tabs,
>  				 struct drm_display_mode *mode)
>  {
> @@ -5236,6 +5257,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
>  	{"i915_energy_uJ", i915_energy_uJ, 0},
>  	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
>  	{"i915_power_domain_info", i915_power_domain_info, 0},
> +	{"i915_dmc_info", i915_dmc_info, 0},
>  	{"i915_display_info", i915_display_info, 0},
>  	{"i915_semaphore_status", i915_semaphore_status, 0},
>  	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
> -- 
> 2.1.4
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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-- 
Ville Syrjälä
Intel OTC
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